29b04fa460
* added breakpoints and stepping * add link register to allow single-stepping a ret instruction, fix stacktraces * refactor to avoid passing the IO layer structs to the breakpoint function * add tests, refine the stacktrace to not include non-function * add register information for core file parsing * core file generation for RISC-V * make tests run under riscv-64 * make tests run under riscv-32
57 lines
1.6 KiB
C
57 lines
1.6 KiB
C
// SPDX-FileCopyrightText: 2010-2011 eloi <limited-entropy.com>
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// SPDX-FileCopyrightText: 2022 Dhruv Maroo <dhruvmaru007@gmail.com>
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// SPDX-License-Identifier: LGPL-3.0-only
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#include <rz_lib.h>
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#include <rz_util.h>
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#include <rz_asm.h>
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#include "asm_private.h"
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#include "sh/disassembler.h"
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#include "sh/assembler.h"
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static int disassemble(const RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
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SHOp *dis_op = sh_disassembler(rz_read_ble16(buf, a->big_endian));
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op->size = 2;
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if (!dis_op) {
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rz_strbuf_set(&op->buf_asm, "invalid");
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} else {
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char *disasm = sh_op_to_str(dis_op, a->pc);
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rz_strbuf_set(&op->buf_asm, disasm);
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free(disasm);
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}
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RZ_FREE(dis_op);
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return op->size;
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}
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static int assemble(const RzAsm *a, RzAsmOp *ao, const char *str) {
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bool success;
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ut16 opcode = sh_assembler(str, a->pc, &success);
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if (!success) {
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return -1;
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}
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ut8 buffer[2];
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rz_write_ble16(buffer, opcode, a->big_endian);
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rz_strbuf_setbin(&ao->buf, buffer, 2);
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return 2;
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}
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static bool sh_sw_breakpoint(const RzAsm *a, ut64 addr, const RzAsmOp *original, RzAsmOp *breakpoint) {
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// { 32, 2, 1, "\xc3\x20" }, // Big endian
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// { 32, 2, 0, "\x20\xc3" }, // Little endian
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rz_asm_op_set_buf(breakpoint, a->big_endian ? (const ut8 *)"\xc3\x20" : (const ut8 *)"\x20\xc3", 2);
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return true;
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}
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RzAsmPlugin rz_asm_plugin_sh = {
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.name = "sh",
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.arch = "sh",
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.author = "DMaroo",
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.license = "LGPL3",
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.bits = 32,
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.endian = RZ_SYS_ENDIAN_LITTLE | RZ_SYS_ENDIAN_BIG,
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.desc = "Hitachi/Renesas SuperH-4 disassembler",
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.disassemble = &disassemble,
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.assemble = &assemble,
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.sw_breakpoint = sh_sw_breakpoint,
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};
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