53a7694631
* Support building for Windows on ARM * Fix usage of reserved function name on ARM * Fix architecture dependent `CONTEXT` fields access * Fixes for debugging on Windows on ARM * Fix breakpoint behavior on windows on ARM * Fix register profile when debugging * Remove `drx` error message if not supported * Add support for hardware breakpoints * Disable support for hardware single-stepping * Fix Windows Message breakpoints on ARM * Fix software single-stepping on return instruction on ARM * Consider link register as destination for return instructions * Fix setting debug bits to 16 * Rename `r12` to `ip` for windows arm register profile * Remove debug bits hardcoding on windows * Add 32bit registers to Windows ARM64 register profile * Fix software step breakpoint alignment when entering thumb mode * Define `RZ_TEST_ARCH` for `arm` and `arm64` * Use `StackWalk64` API for backtracing on Windows * Fix software single-stepping ARM in thumb mode * Sync `asm.bits` with debugger * Cleanup windows_debug.c * Add SPDX for cross-arm64-windows.txt * Add floating point control register flags * Fix Windows Arm register profile alignment * Keep `drx` warning
211 lines
4.3 KiB
C
211 lines
4.3 KiB
C
// SPDX-FileCopyrightText: 2015 pancake <pancake@nopcode.org>
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// SPDX-License-Identifier: LGPL-3.0-only
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// NGREG 34
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return strdup(
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"=PC pc\n"
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"=BP x29\n"
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"=SP sp\n"
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"=LR x30\n"
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"=SN x8\n"
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"=A0 x0\n"
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"=A1 x1\n"
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"=A2 x2\n"
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"=A3 x3\n"
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"=ZF zf\n"
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"=SF nf\n"
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"=OF vf\n"
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"=CF cf\n"
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#if 0
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"=SN ox8\n"
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#endif
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"gpr x0 .64 0 0\n"
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"gpr x1 .64 8 0\n"
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"gpr x2 .64 16 0\n"
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"gpr x3 .64 24 0\n"
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"gpr x4 .64 32 0\n"
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"gpr x5 .64 40 0\n"
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"gpr x6 .64 48 0\n"
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"gpr x7 .64 56 0\n"
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"gpr x8 .64 64 0\n"
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"gpr x9 .64 72 0\n"
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"gpr x10 .64 80 0\n"
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"gpr x11 .64 88 0\n"
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"gpr x12 .64 96 0\n"
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"gpr x13 .64 104 0\n"
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"gpr x14 .64 112 0\n"
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"gpr x15 .64 120 0\n"
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"gpr x16 .64 128 0\n"
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"gpr x17 .64 136 0\n"
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"gpr x18 .64 144 0\n"
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"gpr x19 .64 152 0\n"
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"gpr x20 .64 160 0\n"
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"gpr x21 .64 168 0\n"
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"gpr x22 .64 176 0\n"
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"gpr x23 .64 184 0\n"
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"gpr x24 .64 192 0\n"
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"gpr x25 .64 200 0\n"
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"gpr x26 .64 208 0\n"
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"gpr x27 .64 216 0\n"
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"gpr x28 .64 224 0\n"
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"gpr x29 .64 232 0\n"
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"gpr x30 .64 240 0\n"
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"gpr sp .64 248 0\n"
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"gpr pc .64 256 0\n"
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// 8 bit
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"gpr b0 .8 0 0\n"
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"gpr b1 .8 8 0\n"
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"gpr b2 .8 16 0\n"
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"gpr b3 .8 24 0\n"
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"gpr b4 .8 32 0\n"
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"gpr b5 .8 40 0\n"
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"gpr b6 .8 48 0\n"
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"gpr b7 .8 56 0\n"
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"gpr b8 .8 64 0\n"
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"gpr b9 .8 72 0\n"
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"gpr b10 .8 80 0\n"
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"gpr b11 .8 88 0\n"
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"gpr b12 .8 96 0\n"
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"gpr b13 .8 104 0\n"
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"gpr b14 .8 112 0\n"
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"gpr b15 .8 120 0\n"
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"gpr b16 .8 128 0\n"
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"gpr b17 .8 136 0\n"
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"gpr b18 .8 144 0\n"
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"gpr b19 .8 152 0\n"
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"gpr b20 .8 160 0\n"
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"gpr b21 .8 168 0\n"
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"gpr b22 .8 176 0\n"
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"gpr b23 .8 184 0\n"
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"gpr b24 .8 192 0\n"
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"gpr b25 .8 200 0\n"
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"gpr b26 .8 208 0\n"
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"gpr b27 .8 216 0\n"
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"gpr b28 .8 224 0\n"
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"gpr b29 .8 232 0\n"
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"gpr b30 .8 240 0\n"
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"gpr bsp .8 248 0\n"
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// 16 bit
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"gpr h0 .16 0 0\n"
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"gpr h1 .16 8 0\n"
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"gpr h2 .16 16 0\n"
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"gpr h3 .16 24 0\n"
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"gpr h4 .16 32 0\n"
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"gpr h5 .16 40 0\n"
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"gpr h6 .16 48 0\n"
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"gpr h7 .16 56 0\n"
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"gpr h8 .16 64 0\n"
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"gpr h9 .16 72 0\n"
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"gpr h10 .16 80 0\n"
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"gpr h11 .16 88 0\n"
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"gpr h12 .16 96 0\n"
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"gpr h13 .16 104 0\n"
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"gpr h14 .16 112 0\n"
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"gpr h15 .16 120 0\n"
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"gpr h16 .16 128 0\n"
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"gpr h17 .16 136 0\n"
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"gpr h18 .16 144 0\n"
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"gpr h19 .16 152 0\n"
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"gpr h20 .16 160 0\n"
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"gpr h21 .16 168 0\n"
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"gpr h22 .16 176 0\n"
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"gpr h23 .16 184 0\n"
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"gpr h24 .16 192 0\n"
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"gpr h25 .16 200 0\n"
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"gpr h26 .16 208 0\n"
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"gpr h27 .16 216 0\n"
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"gpr h28 .16 224 0\n"
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"gpr h29 .16 232 0\n"
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"gpr h30 .16 240 0\n"
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// 32 bit
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"gpr w0 .32 0 0\n"
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"gpr w1 .32 8 0\n"
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"gpr w2 .32 16 0\n"
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"gpr w3 .32 24 0\n"
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"gpr w4 .32 32 0\n"
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"gpr w5 .32 40 0\n"
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"gpr w6 .32 48 0\n"
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"gpr w7 .32 56 0\n"
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"gpr w8 .32 64 0\n"
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"gpr w9 .32 72 0\n"
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"gpr w10 .32 80 0\n"
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"gpr w11 .32 88 0\n"
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"gpr w12 .32 96 0\n"
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"gpr w13 .32 104 0\n"
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"gpr w14 .32 112 0\n"
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"gpr w15 .32 120 0\n"
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"gpr w16 .32 128 0\n"
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"gpr w17 .32 136 0\n"
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"gpr w18 .32 144 0\n"
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"gpr w19 .32 152 0\n"
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"gpr w20 .32 160 0\n"
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"gpr w21 .32 168 0\n"
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"gpr w22 .32 176 0\n"
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"gpr w23 .32 184 0\n"
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"gpr w24 .32 192 0\n"
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"gpr w25 .32 200 0\n"
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"gpr w26 .32 208 0\n"
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"gpr w27 .32 216 0\n"
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"gpr w28 .32 224 0\n"
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"gpr w29 .32 232 0\n"
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"gpr w30 .32 240 0\n"
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"gpr wsp .32 248 0\n"
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"gpr wzr .32 ? 0\n"
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"gpr d0 .64 0 0\n"
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"gpr d1 .64 8 0\n"
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"gpr d2 .64 16 0\n"
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"gpr d3 .64 24 0\n"
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"gpr d4 .64 32 0\n"
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"gpr d5 .64 40 0\n"
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"gpr d6 .64 48 0\n"
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"gpr d7 .64 56 0\n"
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"gpr d8 .64 64 0\n"
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"gpr d9 .64 72 0\n"
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"gpr d10 .64 80 0\n"
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"gpr d11 .64 88 0\n"
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"gpr d12 .64 96 0\n"
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"gpr d13 .64 104 0\n"
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"gpr d14 .64 112 0\n"
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"gpr d15 .64 120 0\n"
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"gpr d16 .64 128 0\n"
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"gpr d17 .64 136 0\n"
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"gpr d18 .64 144 0\n"
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"gpr d19 .64 152 0\n"
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"gpr d20 .64 160 0\n"
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"gpr d21 .64 168 0\n"
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"gpr d22 .64 176 0\n"
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"gpr d23 .64 184 0\n"
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"gpr d24 .64 192 0\n"
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"gpr d25 .64 200 0\n"
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"gpr d26 .64 208 0\n"
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"gpr d27 .64 216 0\n"
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"gpr d28 .64 224 0\n"
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"gpr d29 .64 232 0\n"
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"gpr d30 .64 240 0\n"
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"gpr dsp .64 248 0\n"
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"gpr pstate .64 264 0\n"
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"flg fstate .64 264 0 _____tfiae_____________j__qvczn\n"
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"flg vf .1 264.28 0 overflow\n"
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"flg cf .1 264.29 0 carry\n"
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"flg zf .1 264.30 0 zero\n"
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"flg nf .1 264.31 0 sign\n"
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// extra linux regs in struct
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//"gpr ox0 .64 272 0\n"
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//"gpr sysno .64 280 0\n"
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// probably wrong
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#if 0
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"gpr nf .1 .256 0 sign\n" // msb bit of last op
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"gpr zf .1 .257 0 zero\n" // set if last op is 0
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"gpr cf .1 .258 0 carry\n" // set if last op carries
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"gpr vf .1 .259 0 overflow\n" // set if overflows
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#endif
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);
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