53a7694631
* Support building for Windows on ARM * Fix usage of reserved function name on ARM * Fix architecture dependent `CONTEXT` fields access * Fixes for debugging on Windows on ARM * Fix breakpoint behavior on windows on ARM * Fix register profile when debugging * Remove `drx` error message if not supported * Add support for hardware breakpoints * Disable support for hardware single-stepping * Fix Windows Message breakpoints on ARM * Fix software single-stepping on return instruction on ARM * Consider link register as destination for return instructions * Fix setting debug bits to 16 * Rename `r12` to `ip` for windows arm register profile * Remove debug bits hardcoding on windows * Add 32bit registers to Windows ARM64 register profile * Fix software step breakpoint alignment when entering thumb mode * Define `RZ_TEST_ARCH` for `arm` and `arm64` * Use `StackWalk64` API for backtracing on Windows * Fix software single-stepping ARM in thumb mode * Sync `asm.bits` with debugger * Cleanup windows_debug.c * Add SPDX for cross-arm64-windows.txt * Add floating point control register flags * Fix Windows Arm register profile alignment * Keep `drx` warning
78 lines
2.7 KiB
C
78 lines
2.7 KiB
C
// SPDX-FileCopyrightText: 2020 GustavoLCR <gugulcr@gmail.com>
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// SPDX-License-Identifier: LGPL-3.0-only
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return strdup(
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"=PC pc\n"
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"=SP sp\n"
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"=BP fp\n"
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"=LR lr\n"
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"=A0 r0\n"
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"=A1 r1\n"
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"=A2 r2\n"
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"=A3 r3\n"
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"=ZF zf\n"
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"=SF nf\n"
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"=OF vf\n"
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"=CF cf\n"
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"gpr r0 .32 4 0\n"
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"gpr r1 .32 8 0\n"
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"gpr r2 .32 12 0\n"
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"gpr r3 .32 16 0\n"
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"gpr r4 .32 20 0\n"
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"gpr r5 .32 24 0\n"
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"gpr r6 .32 28 0\n"
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"gpr r7 .32 32 0\n"
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"gpr r8 .32 36 0\n"
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"gpr r9 .32 40 0\n"
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"gpr r10 .32 44 0\n"
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"gpr r11 .32 48 0\n"
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"gpr ip .32 52 0\n"
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"gpr sp .32 56 0\n"
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"gpr lr .32 60 0\n"
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"gpr pc .32 64 0\n"
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"flg cpsr .32 68 0 _____tfiae_____________j__qvczn\n"
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"flg vf .1 68.28 0 overflow\n"
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"flg cf .1 68.29 0 carry\n"
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"flg zf .1 68.30 0 zero\n"
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"flg nf .1 68.31 0 sign\n"
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"flg fpscr .32 72 0\n"
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"flg fvf .1 72.28 0 overflow\n"
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"flg fcf .1 72.29 0 carry\n"
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"flg fzf .1 72.30 0 zero\n"
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"flg fnf .1 72.31 0 sign\n"
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"fpu q0 .128 80 0\n"
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"fpu q1 .128 96 0\n"
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"fpu q2 .128 112 0\n"
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"fpu q3 .128 128 0\n"
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"fpu q4 .128 144 0\n"
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"fpu q5 .128 160 0\n"
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"fpu q6 .128 176 0\n"
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"fpu q7 .128 192 0\n"
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"fpu q8 .128 208 0\n"
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"fpu q9 .128 224 0\n"
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"fpu q10 .128 240 0\n"
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"fpu q11 .128 256 0\n"
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"fpu q12 .128 272 0\n"
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"fpu q13 .128 288 0\n"
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"fpu q14 .128 304 0\n"
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"fpu q15 .128 320 0\n"
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"drx bcr0 .32 336 0\n"
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"drx bcr1 .32 340 0\n"
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"drx bcr2 .32 344 0\n"
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"drx bcr3 .32 348 0\n"
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"drx bcr4 .32 352 0\n"
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"drx bcr5 .32 356 0\n"
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"drx bcr6 .32 360 0\n"
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"drx bcr7 .32 364 0\n"
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"drx bvr0 .32 368 0\n"
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"drx bvr1 .32 372 0\n"
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"drx bvr2 .32 376 0\n"
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"drx bvr3 .32 380 0\n"
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"drx bvr4 .32 384 0\n"
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"drx bvr5 .32 388 0\n"
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"drx bvr6 .32 392 0\n"
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"drx bvr7 .32 396 0\n"
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"drx wcr0 .32 400 0\n"
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"drx wcr1 .32 404 0\n"
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"drx wvr0 .32 408 0\n"
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"drx wvr1 .32 412 0\n");
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