53a7694631
* Support building for Windows on ARM * Fix usage of reserved function name on ARM * Fix architecture dependent `CONTEXT` fields access * Fixes for debugging on Windows on ARM * Fix breakpoint behavior on windows on ARM * Fix register profile when debugging * Remove `drx` error message if not supported * Add support for hardware breakpoints * Disable support for hardware single-stepping * Fix Windows Message breakpoints on ARM * Fix software single-stepping on return instruction on ARM * Consider link register as destination for return instructions * Fix setting debug bits to 16 * Rename `r12` to `ip` for windows arm register profile * Remove debug bits hardcoding on windows * Add 32bit registers to Windows ARM64 register profile * Fix software step breakpoint alignment when entering thumb mode * Define `RZ_TEST_ARCH` for `arm` and `arm64` * Use `StackWalk64` API for backtracing on Windows * Fix software single-stepping ARM in thumb mode * Sync `asm.bits` with debugger * Cleanup windows_debug.c * Add SPDX for cross-arm64-windows.txt * Add floating point control register flags * Fix Windows Arm register profile alignment * Keep `drx` warning
233 lines
No EOL
8.6 KiB
C
233 lines
No EOL
8.6 KiB
C
// SPDX-FileCopyrightText: 2020 GustavoLCR <gugulcr@gmail.com>
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// SPDX-License-Identifier: LGPL-3.0-only
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if (dbg->bits == RZ_SYS_BITS_64) {
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return strdup(
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"=PC pc\n"
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"=SP sp\n"
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"=BP fp\n"
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"=LR lr\n"
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"=A0 x0\n"
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"=A1 x1\n"
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"=A2 x2\n"
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"=A3 x3\n"
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"=ZF zf\n"
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"=SF nf\n"
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"=OF vf\n"
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"=CF cf\n"
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"=SN x16\n"
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"flg cpsr .32 4 0 _____tfiae_____________j__qvczn\n"
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"flg vf .1 4.28 0 overflow\n"
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"flg cf .1 4.29 0 carry\n"
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"flg zf .1 4.30 0 zero\n"
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"flg nf .1 4.31 0 sign\n"
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"gpr x0 .64 8 0\n"
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"gpr x1 .64 16 0\n"
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"gpr x2 .64 24 0\n"
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"gpr x3 .64 32 0\n"
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"gpr x4 .64 40 0\n"
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"gpr x5 .64 48 0\n"
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"gpr x6 .64 56 0\n"
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"gpr x7 .64 64 0\n"
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"gpr x8 .64 72 0\n"
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"gpr x9 .64 80 0\n"
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"gpr x10 .64 88 0\n"
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"gpr x11 .64 96 0\n"
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"gpr x12 .64 104 0\n"
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"gpr x13 .64 112 0\n"
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"gpr x14 .64 120 0\n"
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"gpr x15 .64 128 0\n"
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"gpr x16 .64 136 0\n"
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"gpr x17 .64 144 0\n"
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"gpr x18 .64 152 0\n"
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"gpr x19 .64 160 0\n"
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"gpr x20 .64 168 0\n"
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"gpr x21 .64 176 0\n"
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"gpr x22 .64 184 0\n"
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"gpr x23 .64 192 0\n"
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"gpr x24 .64 200 0\n"
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"gpr x25 .64 208 0\n"
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"gpr x26 .64 216 0\n"
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"gpr x27 .64 224 0\n"
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"gpr x28 .64 232 0\n"
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"gpr w0 .32 8 0\n"
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"gpr w1 .32 16 0\n"
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"gpr w2 .32 24 0\n"
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"gpr w3 .32 32 0\n"
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"gpr w4 .32 40 0\n"
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"gpr w5 .32 48 0\n"
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"gpr w6 .32 56 0\n"
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"gpr w7 .32 64 0\n"
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"gpr w8 .32 72 0\n"
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"gpr w9 .32 80 0\n"
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"gpr w10 .32 88 0\n"
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"gpr w11 .32 96 0\n"
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"gpr w12 .32 104 0\n"
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"gpr w13 .32 112 0\n"
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"gpr w14 .32 120 0\n"
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"gpr w15 .32 128 0\n"
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"gpr w16 .32 136 0\n"
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"gpr w17 .32 144 0\n"
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"gpr w18 .32 152 0\n"
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"gpr w19 .32 160 0\n"
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"gpr w20 .32 168 0\n"
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"gpr w21 .32 176 0\n"
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"gpr w22 .32 184 0\n"
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"gpr w23 .32 192 0\n"
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"gpr w24 .32 200 0\n"
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"gpr w25 .32 208 0\n"
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"gpr w26 .32 216 0\n"
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"gpr w27 .32 224 0\n"
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"gpr w28 .32 232 0\n"
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"gpr fp .64 240 0\n"
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"gpr lr .64 248 0\n"
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"gpr sp .64 256 0\n"
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"gpr pc .64 264 0\n"
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"fpu v0 .128 272 0\n"
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"fpu v1 .128 288 0\n"
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"fpu v2 .128 304 0\n"
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"fpu v3 .128 320 0\n"
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"fpu v4 .128 336 0\n"
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"fpu v5 .128 352 0\n"
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"fpu v6 .128 368 0\n"
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"fpu v7 .128 384 0\n"
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"fpu v8 .128 400 0\n"
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"fpu v9 .128 416 0\n"
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"fpu v10 .128 432 0\n"
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"fpu v11 .128 448 0\n"
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"fpu v12 .128 464 0\n"
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"fpu v13 .128 480 0\n"
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"fpu v14 .128 496 0\n"
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"fpu v15 .128 512 0\n"
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"fpu v16 .128 528 0\n"
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"fpu v17 .128 544 0\n"
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"fpu v18 .128 560 0\n"
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"fpu v19 .128 576 0\n"
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"fpu v20 .128 592 0\n"
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"fpu v21 .128 608 0\n"
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"fpu v22 .128 624 0\n"
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"fpu v23 .128 640 0\n"
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"fpu v24 .128 656 0\n"
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"fpu v25 .128 672 0\n"
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"fpu v26 .128 688 0\n"
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"fpu v27 .128 704 0\n"
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"fpu v28 .128 720 0\n"
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"fpu v29 .128 736 0\n"
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"fpu v30 .128 752 0\n"
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"fpu v31 .128 768 0\n"
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"flg fpcr .32 784 0\n"
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"flg fpsr .32 788 0\n"
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"flg fvf .1 788.28 0 overflow\n"
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"flg fcf .1 788.29 0 carry\n"
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"flg fzf .1 788.30 0 zero\n"
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"flg fnf .1 788.31 0 sign\n"
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"drx bcr0 .32 792 0\n"
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"drx bcr1 .32 796 0\n"
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"drx bcr2 .32 800 0\n"
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"drx bcr3 .32 804 0\n"
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"drx bcr4 .32 808 0\n"
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"drx bcr5 .32 812 0\n"
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"drx bcr6 .32 816 0\n"
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"drx bcr7 .32 820 0\n"
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"drx bvr0 .64 824 0\n"
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"drx bvr1 .64 832 0\n"
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"drx bvr2 .64 840 0\n"
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"drx bvr3 .64 848 0\n"
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"drx bvr4 .64 856 0\n"
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"drx bvr5 .64 864 0\n"
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"drx bvr6 .64 872 0\n"
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"drx bvr7 .64 880 0\n"
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"drx wcr0 .32 888 0\n"
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"drx wcr1 .32 892 0\n"
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"drx wvr0 .64 896 0\n"
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"drx wvr1 .64 904 0\n");
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} else {
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return strdup(
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"=PC pc\n"
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"=SP sp\n"
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"=BP fp\n"
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"=LR lr\n"
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"=A0 r0\n"
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"=A1 r1\n"
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"=A2 r2\n"
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"=A3 r3\n"
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"=ZF zf\n"
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"=SF nf\n"
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"=OF vf\n"
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"=CF cf\n"
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"flg cpsr .32 4 0 _____tfiae_____________j__qvczn\n"
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"flg vf .1 4.28 0 overflow\n"
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"flg cf .1 4.29 0 carry\n"
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"flg zf .1 4.30 0 zero\n"
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"flg nf .1 4.31 0 sign\n"
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"gpr r0 .32 8 0\n"
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"gpr r1 .32 16 0\n"
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"gpr r2 .32 24 0\n"
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"gpr r3 .32 32 0\n"
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"gpr r4 .32 40 0\n"
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"gpr r5 .32 48 0\n"
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"gpr r6 .32 56 0\n"
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"gpr r7 .32 64 0\n"
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"gpr r8 .32 72 0\n"
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"gpr r9 .32 80 0\n"
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"gpr r10 .32 88 0\n"
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"gpr fp .32 96 0\n"
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"gpr ip .32 104 0\n"
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"gpr sp .32 112 0\n"
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"gpr lr .32 120 0\n"
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"gpr pc .64 264 0\n"
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"fpu v0 .128 272 0\n"
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"fpu v1 .128 288 0\n"
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"fpu v2 .128 304 0\n"
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"fpu v3 .128 320 0\n"
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"fpu v4 .128 336 0\n"
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"fpu v5 .128 352 0\n"
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"fpu v6 .128 368 0\n"
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"fpu v7 .128 384 0\n"
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"fpu v8 .128 400 0\n"
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"fpu v9 .128 416 0\n"
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"fpu v10 .128 432 0\n"
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"fpu v11 .128 448 0\n"
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"fpu v12 .128 464 0\n"
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"fpu v13 .128 480 0\n"
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"fpu v14 .128 496 0\n"
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"fpu v15 .128 512 0\n"
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"fpu v16 .128 528 0\n"
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"fpu v17 .128 544 0\n"
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"fpu v18 .128 560 0\n"
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"fpu v19 .128 576 0\n"
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"fpu v20 .128 592 0\n"
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"fpu v21 .128 608 0\n"
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"fpu v22 .128 624 0\n"
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"fpu v23 .128 640 0\n"
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"fpu v24 .128 656 0\n"
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"fpu v25 .128 672 0\n"
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"fpu v26 .128 688 0\n"
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"fpu v27 .128 704 0\n"
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"fpu v28 .128 720 0\n"
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"fpu v29 .128 736 0\n"
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"fpu v30 .128 752 0\n"
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"fpu v31 .128 768 0\n"
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"gpr fpcr .32 784 0\n"
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"gpr fpsr .32 788 0\n"
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"drx bcr0 .32 792 0\n"
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"drx bcr1 .32 796 0\n"
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"drx bcr2 .32 800 0\n"
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"drx bcr3 .32 804 0\n"
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"drx bcr4 .32 808 0\n"
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"drx bcr5 .32 812 0\n"
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"drx bcr6 .32 816 0\n"
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"drx bcr7 .32 820 0\n"
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"drx bvr0 .64 824 0\n"
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"drx bvr1 .64 832 0\n"
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"drx bvr2 .64 840 0\n"
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"drx bvr3 .64 848 0\n"
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"drx bvr4 .64 856 0\n"
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"drx bvr5 .64 864 0\n"
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"drx bvr6 .64 872 0\n"
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"drx bvr7 .64 880 0\n"
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"drx wcr0 .32 888 0\n"
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"drx wcr1 .32 892 0\n"
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"drx wvr0 .64 896 0\n"
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"drx wvr1 .64 904 0\n");
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} |