53bf5c497f
- Add LICENSES directory - Download additional licenses used - Add .reuse directory - Add doc about SPDX/reuse Co-authored-by: Florian Märkl <info@florianmaerkl.de>
621 lines
16 KiB
C
621 lines
16 KiB
C
// SPDX-FileCopyrightText: 2013-2020 pancake <pancake@nopcode.org>
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// SPDX-License-Identifier: LGPL-3.0-only
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#include <rz_asm.h>
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#include <rz_lib.h>
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#if CSNEXT
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#include <capstone.h>
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#include <riscv.h>
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// http://www.mrc.uidaho.edu/mrc/people/jff/digital/RISCVir.html
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#define OPERAND(x) insn->detail->riscv.operands[x]
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#define REGID(x) insn->detail->riscv.operands[x].reg
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#define REG(x) cs_reg_name(*handle, insn->detail->riscv.operands[x].reg)
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#define IMM(x) insn->detail->riscv.operands[x].imm
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#define MEMBASE(x) cs_reg_name(*handle, insn->detail->riscv.operands[x].mem.base)
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#define MEMINDEX(x) insn->detail->riscv.operands[x].mem.index
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#define MEMDISP(x) insn->detail->riscv.operands[x].mem.disp
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#define OPCOUNT() insn->detail->riscv.op_count
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// TODO scale and disp
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#define SET_VAL(op, i) \
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if ((i) < OPCOUNT() && OPERAND(i).type == RISCV_OP_IMM) { \
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(op)->val = OPERAND(i).imm; \
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}
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#define CREATE_SRC_DST_3(op) \
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(op)->src[0] = rz_analysis_value_new(); \
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(op)->src[1] = rz_analysis_value_new(); \
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(op)->dst = rz_analysis_value_new();
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#define CREATE_SRC_DST_2(op) \
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(op)->src[0] = rz_analysis_value_new(); \
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(op)->dst = rz_analysis_value_new();
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#define SET_SRC_DST_3_REGS(op) \
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CREATE_SRC_DST_3(op); \
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(op)->dst->reg = rz_reg_get(analysis->reg, REG(0), RZ_REG_TYPE_GPR); \
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(op)->src[0]->reg = rz_reg_get(analysis->reg, REG(1), RZ_REG_TYPE_GPR); \
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(op)->src[1]->reg = rz_reg_get(analysis->reg, REG(2), RZ_REG_TYPE_GPR);
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#define SET_SRC_DST_3_IMM(op) \
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CREATE_SRC_DST_3(op); \
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(op)->dst->reg = rz_reg_get(analysis->reg, REG(0), RZ_REG_TYPE_GPR); \
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(op)->src[0]->reg = rz_reg_get(analysis->reg, REG(1), RZ_REG_TYPE_GPR); \
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(op)->src[1]->imm = IMM(2);
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#define SET_SRC_DST_2_REGS(op) \
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CREATE_SRC_DST_2(op); \
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(op)->dst->reg = rz_reg_get(analysis->reg, REG(0), RZ_REG_TYPE_GPR); \
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(op)->src[0]->reg = rz_reg_get(analysis->reg, REG(1), RZ_REG_TYPE_GPR);
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#define SET_SRC_DST_3_REG_OR_IMM(op) \
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if (OPERAND(2).type == RISCV_OP_IMM) { \
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SET_SRC_DST_3_IMM(op); \
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} else if (OPERAND(2).type == RISCV_OP_REG) { \
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SET_SRC_DST_3_REGS(op); \
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}
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// ESIL macros:
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// put the sign bit on the stack
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#define ES_IS_NEGATIVE(arg) "1," arg ",<<<,1,&"
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// call with delay slot
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#define ES_CALL_DR(ra, addr) "pc,4,+," ra ",=," ES_J(addr)
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#define ES_CALL_D(addr) ES_CALL_DR("ra", addr)
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// call without delay slot
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#define ES_CALL_NDR(ra, addr) "pc," ra ",=," ES_J(addr)
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#define ES_CALL_ND(addr) ES_CALL_NDR("ra", addr)
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#define USE_DS 0
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#if USE_DS
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// emit ERR trap if executed in a delay slot
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#define ES_TRAP_DS() "$ds,!,!,?{,$$,1,TRAP,BREAK,},"
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// jump to address
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#define ES_J(addr) addr ",SETJT,1,SETD"
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#else
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#define ES_TRAP_DS() ""
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#define ES_J(addr) addr ",pc,="
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#endif
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// sign extend 32 -> 64
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#define ES_SIGN_EXT64(arg) \
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arg ",0x80000000,&,0,<,?{," \
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"0xffffffff00000000," arg ",|=," \
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"}"
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#define PROTECT_ZERO() \
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if (REG(0)[0] == 'z') { \
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rz_strbuf_appendf(&op->esil, ","); \
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} else
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#define ESIL_LOAD(size) \
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PROTECT_ZERO() { \
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rz_strbuf_appendf(&op->esil, "%s,[" size "],%s,=", \
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ARG(1), REG(0)); \
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}
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static void opex(RzStrBuf *buf, csh handle, cs_insn *insn) {
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int i;
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PJ *pj = pj_new();
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if (!pj) {
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return:
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}
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pj_o(pj);
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pj_ka(pj, "operands");
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cs_riscv *x = &insn->detail->riscv;
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for (i = 0; i < x->op_count; i++) {
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cs_riscv_op *op = x->operands + i;
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pj_o(pj);
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switch (op->type) {
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case RISCV_OP_REG:
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pj_ks(pj, "type", "reg");
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pj_ks(pj, "value", cs_reg_name(handle, op->reg));
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break;
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case RISCV_OP_IMM:
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pj_ks(pj, "type", "imm");
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pj_kN(pj, "value", op->imm);
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break;
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case RISCV_OP_MEM:
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pj_ks(pj, "type", "mem");
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if (op->mem.base != RISCV_REG_INVALID) {
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pj_ks(pj, "base", cs_reg_name(handle, op->mem.base));
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}
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pj_kN(pj, "disp", op->mem.disp);
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break;
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default:
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pj_ks(pj, "type", "invalid");
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break;
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}
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pj_end(pj); /* o operand */
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}
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pj_end(pj); /* a operands */
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pj_end(pj);
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rz_strbuf_init(buf);
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rz_strbuf_append(buf, pj_string(pj));
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pj_free(pj);
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}
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static const char *arg(csh *handle, cs_insn *insn, char *buf, int n) {
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*buf = 0;
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switch (insn->detail->riscv.operands[n].type) {
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case RISCV_OP_INVALID:
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break;
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case RISCV_OP_REG:
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sprintf(buf, "%s",
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cs_reg_name(*handle,
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insn->detail->riscv.operands[n].reg));
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break;
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case RISCV_OP_IMM: {
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st64 x = (st64)insn->detail->riscv.operands[n].imm;
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sprintf(buf, "%" PFMT64d, x);
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break;
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}
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case RISCV_OP_MEM: {
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st64 disp = insn->detail->riscv.operands[n].mem.disp;
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if (disp < 0) {
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sprintf(buf, "%" PFMT64d ",%s,-",
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(ut64)-insn->detail->riscv.operands[n].mem.disp,
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cs_reg_name(*handle,
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insn->detail->riscv.operands[n].mem.base));
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} else {
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sprintf(buf, "0x%" PFMT64x ",%s,+",
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insn->detail->riscv.operands[n].mem.disp,
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cs_reg_name(*handle,
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insn->detail->riscv.operands[n].mem.base));
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}
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break;
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}
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}
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return buf;
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}
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#define ARG(x) (*str[x] != 0) ? str[x] : arg(handle, insn, str[x], x)
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static int analop_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn) {
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char str[8][32] = { { 0 } };
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int i;
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rz_strbuf_init(&op->esil);
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rz_strbuf_set(&op->esil, "");
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if (insn) {
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// caching operands
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for (i = 0; i < insn->detail->riscv.op_count && i < 8; i++) {
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*str[i] = 0;
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ARG(i);
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}
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}
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switch (insn->id) {
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//case RISCV_INS_NOP:
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// rz_strbuf_setf (&op->esil, ",");
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// break;
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}
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return 0;
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}
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static int parse_reg_name(RzRegItem *reg, csh handle, cs_insn *insn, int reg_num) {
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if (!reg) {
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return -1;
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}
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switch (OPERAND(reg_num).type) {
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case RISCV_OP_REG:
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reg->name = (char *)cs_reg_name(handle, OPERAND(reg_num).reg);
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break;
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case RISCV_OP_MEM:
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if (OPERAND(reg_num).mem.base != RISCV_REG_INVALID) {
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reg->name = (char *)cs_reg_name(handle, OPERAND(reg_num).mem.base);
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}
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default:
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break;
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}
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return 0;
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}
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static void op_fillval(RzAnalysis *analysis, RzAnalysisOp *op, csh *handle, cs_insn *insn) {
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static RzRegItem reg;
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switch (op->type & RZ_ANALYSIS_OP_TYPE_MASK) {
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case RZ_ANALYSIS_OP_TYPE_LOAD:
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if (OPERAND(1).type == RISCV_OP_MEM) {
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ZERO_FILL(reg);
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op->src[0] = rz_analysis_value_new();
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op->src[0]->reg = ®
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parse_reg_name(op->src[0]->reg, *handle, insn, 1);
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op->src[0]->delta = OPERAND(1).mem.disp;
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}
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break;
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case RZ_ANALYSIS_OP_TYPE_STORE:
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if (OPERAND(1).type == RISCV_OP_MEM) {
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ZERO_FILL(reg);
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op->dst = rz_analysis_value_new();
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op->dst->reg = ®
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parse_reg_name(op->dst->reg, *handle, insn, 1);
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op->dst->delta = OPERAND(1).mem.disp;
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}
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break;
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case RZ_ANALYSIS_OP_TYPE_SHL:
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case RZ_ANALYSIS_OP_TYPE_SHR:
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case RZ_ANALYSIS_OP_TYPE_SAR:
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case RZ_ANALYSIS_OP_TYPE_XOR:
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case RZ_ANALYSIS_OP_TYPE_SUB:
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case RZ_ANALYSIS_OP_TYPE_AND:
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case RZ_ANALYSIS_OP_TYPE_ADD:
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case RZ_ANALYSIS_OP_TYPE_OR:
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SET_SRC_DST_3_REG_OR_IMM(op);
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break;
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case RZ_ANALYSIS_OP_TYPE_MOV:
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SET_SRC_DST_3_REG_OR_IMM(op);
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break;
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case RZ_ANALYSIS_OP_TYPE_DIV: // UDIV
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#if 0
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capstone bug
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------------
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$ rizin -a riscv -e cfg.bigendian=1 -c "wx 0083001b" -
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// should be 3 regs, right?
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[0x00000000]> aoj~{}
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[
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{
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"opcode": "divu zero, a0, v1",
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"disasm": "divu zero, a0, v1",
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"mnemonic": "divu",
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"sign": false,
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"prefix": 0,
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"id": 192,
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"opex": {
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"operands": [
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{
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"type": "reg",
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"value": "a0"
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},
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{
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"type": "reg",
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"value": "v1"
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}
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]
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},
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#endif
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if (OPERAND(0).type == RISCV_OP_REG && OPERAND(1).type == RISCV_OP_REG && OPERAND(2).type == RISCV_OP_REG) {
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SET_SRC_DST_3_REGS(op);
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} else if (OPERAND(0).type == RISCV_OP_REG && OPERAND(1).type == RISCV_OP_REG) {
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SET_SRC_DST_2_REGS(op);
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} else {
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eprintf("Unknown div at 0x%08" PFMT64x "\n", op->addr);
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}
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break;
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}
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if (insn && (insn->id == RISCV_INS_SLTI || insn->id == RISCV_INS_SLTIU)) {
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SET_SRC_DST_3_IMM(op);
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}
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}
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static void set_opdir(RzAnalysisOp *op) {
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switch (op->type & RZ_ANALYSIS_OP_TYPE_MASK) {
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case RZ_ANALYSIS_OP_TYPE_LOAD:
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op->direction = RZ_ANALYSIS_OP_DIR_READ;
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break;
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case RZ_ANALYSIS_OP_TYPE_STORE:
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op->direction = RZ_ANALYSIS_OP_DIR_WRITE;
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break;
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case RZ_ANALYSIS_OP_TYPE_LEA:
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op->direction = RZ_ANALYSIS_OP_DIR_REF;
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break;
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case RZ_ANALYSIS_OP_TYPE_CALL:
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case RZ_ANALYSIS_OP_TYPE_JMP:
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case RZ_ANALYSIS_OP_TYPE_UJMP:
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case RZ_ANALYSIS_OP_TYPE_UCALL:
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op->direction = RZ_ANALYSIS_OP_DIR_EXEC;
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break;
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default:
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break;
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}
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}
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static int analop(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask) {
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int n, ret, opsize = -1;
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static csh hndl = 0;
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static int omode = -1;
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static int obits = 32;
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cs_insn *insn;
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int mode = (analysis->bits == 64) ? CS_MODE_RISCV64 : CS_MODE_RISCV32;
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if (mode != omode || analysis->bits != obits) {
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cs_close(&hndl);
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hndl = 0;
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omode = mode;
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obits = analysis->bits;
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}
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// XXX no arch->cpu ?!?! CS_MODE_MICRO, N64
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op->addr = addr;
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if (len < 4) {
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return -1;
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}
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op->size = 4;
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if (hndl == 0) {
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ret = cs_open(CS_ARCH_RISCV, mode, &hndl);
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if (ret != CS_ERR_OK) {
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goto fin;
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}
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cs_option(hndl, CS_OPT_DETAIL, CS_OPT_ON);
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}
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n = cs_disasm(hndl, (ut8 *)buf, len, addr, 1, &insn);
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if (n < 1 || insn->size < 1) {
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goto beach;
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}
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op->id = insn->id;
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opsize = op->size = insn->size;
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switch (insn->id) {
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case RISCV_INS_C_NOP:
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op->type = RZ_ANALYSIS_OP_TYPE_NOP;
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break;
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case RISCV_INS_INVALID:
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op->type = RZ_ANALYSIS_OP_TYPE_ILL;
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break;
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case RISCV_INS_C_JALR:
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op->type = RZ_ANALYSIS_OP_TYPE_UCALL;
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break;
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case RISCV_INS_C_JR:
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op->type = RZ_ANALYSIS_OP_TYPE_UJMP;
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break;
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case RISCV_INS_C_MV:
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op->type = RZ_ANALYSIS_OP_TYPE_MOV;
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break;
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case RISCV_INS_JAL:
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op->type = RZ_ANALYSIS_OP_TYPE_CALL;
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op->jump = IMM(0);
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op->fail = op->addr + op->size;
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break;
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case RISCV_INS_MRET:
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case RISCV_INS_SRET:
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case RISCV_INS_URET:
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op->type = RZ_ANALYSIS_OP_TYPE_RET;
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break;
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}
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beach:
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set_opdir(op);
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if (insn && mask & RZ_ANALYSIS_OP_MASK_OPEX) {
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opex(&op->opex, hndl, insn);
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}
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if (mask & RZ_ANALYSIS_OP_MASK_ESIL) {
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if (analop_esil(analysis, op, addr, buf, len, &hndl, insn) != 0) {
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rz_strbuf_fini(&op->esil);
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}
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}
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if (mask & RZ_ANALYSIS_OP_MASK_VAL) {
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op_fillval(analysis, op, &hndl, insn);
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}
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cs_free(insn, n);
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//cs_close (&handle);
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fin:
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return opsize;
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}
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static char *get_reg_profile(RzAnalysis *analysis) {
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const char *p = NULL;
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switch (analysis->bits) {
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case 32:
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p =
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"=PC pc\n"
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"=SP sp\n" // ABI: stack pointer
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"=LR ra\n" // ABI: return address
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"=BP s0\n" // ABI: frame pointer
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"=A0 a0\n"
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"=A1 a1\n"
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"gpr pc .32 0 0\n"
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// RV32I regs (ABI names)
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// From user-Level ISA Specification, section 2.1
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// "zero" has been left out as it ignores writes and always reads as zero
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"gpr ra .32 4 0\n" // =x1
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"gpr sp .32 8 0\n" // =x2
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"gpr gp .32 12 0\n" // =x3
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"gpr tp .32 16 0\n" // =x4
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"gpr t0 .32 20 0\n" // =x5
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"gpr t1 .32 24 0\n" // =x6
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"gpr t2 .32 28 0\n" // =x7
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"gpr s0 .32 32 0\n" // =x8
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"gpr s1 .32 36 0\n" // =x9
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"gpr a0 .32 40 0\n" // =x10
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"gpr a1 .32 44 0\n" // =x11
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"gpr a2 .32 48 0\n" // =x12
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"gpr a3 .32 52 0\n" // =x13
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"gpr a4 .32 56 0\n" // =x14
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"gpr a5 .32 60 0\n" // =x15
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"gpr a6 .32 64 0\n" // =x16
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"gpr a7 .32 68 0\n" // =x17
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"gpr s2 .32 72 0\n" // =x18
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"gpr s3 .32 76 0\n" // =x19
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"gpr s4 .32 80 0\n" // =x20
|
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"gpr s5 .32 84 0\n" // =x21
|
|
"gpr s6 .32 88 0\n" // =x22
|
|
"gpr s7 .32 92 0\n" // =x23
|
|
"gpr s8 .32 96 0\n" // =x24
|
|
"gpr s9 .32 100 0\n" // =x25
|
|
"gpr s10 .32 104 0\n" // =x26
|
|
"gpr s11 .32 108 0\n" // =x27
|
|
"gpr t3 .32 112 0\n" // =x28
|
|
"gpr t4 .32 116 0\n" // =x29
|
|
"gpr t5 .32 120 0\n" // =x30
|
|
"gpr t6 .32 124 0\n" // =x31
|
|
// RV32F/D regs (ABI names)
|
|
// From user-Level ISA Specification, section 8.1 and 9.1
|
|
"gpr ft0 .64 128 0\n" // =f0
|
|
"gpr ft1 .64 136 0\n" // =f1
|
|
"gpr ft2 .64 144 0\n" // =f2
|
|
"gpr ft3 .64 152 0\n" // =f3
|
|
"gpr ft4 .64 160 0\n" // =f4
|
|
"gpr ft5 .64 168 0\n" // =f5
|
|
"gpr ft6 .64 176 0\n" // =f6
|
|
"gpr ft7 .64 184 0\n" // =f7
|
|
"gpr fs0 .64 192 0\n" // =f8
|
|
"gpr fs1 .64 200 0\n" // =f9
|
|
"gpr fa0 .64 208 0\n" // =f10
|
|
"gpr fa1 .64 216 0\n" // =f11
|
|
"gpr fa2 .64 224 0\n" // =f12
|
|
"gpr fa3 .64 232 0\n" // =f13
|
|
"gpr fa4 .64 240 0\n" // =f14
|
|
"gpr fa5 .64 248 0\n" // =f15
|
|
"gpr fa6 .64 256 0\n" // =f16
|
|
"gpr fa7 .64 264 0\n" // =f17
|
|
"gpr fs2 .64 272 0\n" // =f18
|
|
"gpr fs3 .64 280 0\n" // =f19
|
|
"gpr fs4 .64 288 0\n" // =f20
|
|
"gpr fs5 .64 296 0\n" // =f21
|
|
"gpr fs6 .64 304 0\n" // =f22
|
|
"gpr fs7 .64 312 0\n" // =f23
|
|
"gpr fs8 .64 320 0\n" // =f24
|
|
"gpr fs9 .64 328 0\n" // =f25
|
|
"gpr fs10 .64 336 0\n" // =f26
|
|
"gpr fs11 .64 344 0\n" // =f27
|
|
"gpr ft8 .64 352 0\n" // =f28
|
|
"gpr ft9 .64 360 0\n" // =f29
|
|
"gpr ft10 .64 368 0\n" // =f30
|
|
"gpr ft11 .64 376 0\n" // =f31
|
|
"gpr fcsr .32 384 0\n"
|
|
"flg nx .1 3072 0\n"
|
|
"flg uf .1 3073 0\n"
|
|
"flg of .1 3074 0\n"
|
|
"flg dz .1 3075 0\n"
|
|
"flg nv .1 3076 0\n"
|
|
"flg frm .3 3077 0\n";
|
|
|
|
break;
|
|
case 64:
|
|
p =
|
|
"=PC pc\n"
|
|
"=SP sp\n" // ABI: stack pointer
|
|
"=LR ra\n" // ABI: return address
|
|
"=BP s0\n" // ABI: frame pointer
|
|
"=A0 a0\n"
|
|
"=A1 a1\n"
|
|
|
|
"gpr pc .64 0 0\n"
|
|
// RV64I regs (ABI names)
|
|
// From user-Level ISA Specification, section 2.1 and 4.1
|
|
// "zero" has been left out as it ignores writes and always reads as zero
|
|
"gpr ra .64 8 0\n" // =x1
|
|
"gpr sp .64 16 0\n" // =x2
|
|
"gpr gp .64 24 0\n" // =x3
|
|
"gpr tp .64 32 0\n" // =x4
|
|
"gpr t0 .64 40 0\n" // =x5
|
|
"gpr t1 .64 48 0\n" // =x6
|
|
"gpr t2 .64 56 0\n" // =x7
|
|
"gpr s0 .64 64 0\n" // =x8
|
|
"gpr s1 .64 72 0\n" // =x9
|
|
"gpr a0 .64 80 0\n" // =x10
|
|
"gpr a1 .64 88 0\n" // =x11
|
|
"gpr a2 .64 96 0\n" // =x12
|
|
"gpr a3 .64 104 0\n" // =x13
|
|
"gpr a4 .64 112 0\n" // =x14
|
|
"gpr a5 .64 120 0\n" // =x15
|
|
"gpr a6 .64 128 0\n" // =x16
|
|
"gpr a7 .64 136 0\n" // =x17
|
|
"gpr s2 .64 144 0\n" // =x18
|
|
"gpr s3 .64 152 0\n" // =x19
|
|
"gpr s4 .64 160 0\n" // =x20
|
|
"gpr s5 .64 168 0\n" // =x21
|
|
"gpr s6 .64 176 0\n" // =x22
|
|
"gpr s7 .64 184 0\n" // =x23
|
|
"gpr s8 .64 192 0\n" // =x24
|
|
"gpr s9 .64 200 0\n" // =x25
|
|
"gpr s10 .64 208 0\n" // =x26
|
|
"gpr s11 .64 216 0\n" // =x27
|
|
"gpr t3 .64 224 0\n" // =x28
|
|
"gpr t4 .64 232 0\n" // =x29
|
|
"gpr t5 .64 240 0\n" // =x30
|
|
"gpr t6 .64 248 0\n" // =x31
|
|
// RV64F/D regs (ABI names)
|
|
"gpr ft0 .64 256 0\n" // =f0
|
|
"gpr ft1 .64 264 0\n" // =f1
|
|
"gpr ft2 .64 272 0\n" // =f2
|
|
"gpr ft3 .64 280 0\n" // =f3
|
|
"gpr ft4 .64 288 0\n" // =f4
|
|
"gpr ft5 .64 296 0\n" // =f5
|
|
"gpr ft6 .64 304 0\n" // =f6
|
|
"gpr ft7 .64 312 0\n" // =f7
|
|
"gpr fs0 .64 320 0\n" // =f8
|
|
"gpr fs1 .64 328 0\n" // =f9
|
|
"gpr fa0 .64 336 0\n" // =f10
|
|
"gpr fa1 .64 344 0\n" // =f11
|
|
"gpr fa2 .64 352 0\n" // =f12
|
|
"gpr fa3 .64 360 0\n" // =f13
|
|
"gpr fa4 .64 368 0\n" // =f14
|
|
"gpr fa5 .64 376 0\n" // =f15
|
|
"gpr fa6 .64 384 0\n" // =f16
|
|
"gpr fa7 .64 392 0\n" // =f17
|
|
"gpr fs2 .64 400 0\n" // =f18
|
|
"gpr fs3 .64 408 0\n" // =f19
|
|
"gpr fs4 .64 416 0\n" // =f20
|
|
"gpr fs5 .64 424 0\n" // =f21
|
|
"gpr fs6 .64 432 0\n" // =f22
|
|
"gpr fs7 .64 440 0\n" // =f23
|
|
"gpr fs8 .64 448 0\n" // =f24
|
|
"gpr fs9 .64 456 0\n" // =f25
|
|
"gpr fs10 .64 464 0\n" // =f26
|
|
"gpr fs11 .64 472 0\n" // =f27
|
|
"gpr ft8 .64 480 0\n" // =f28
|
|
"gpr ft9 .64 488 0\n" // =f29
|
|
"gpr ft10 .64 496 0\n" // =f30
|
|
"gpr ft11 .64 504 0\n" // =f31
|
|
"gpr fcsr .32 512 0\n"
|
|
"flg nx .1 4096 0\n"
|
|
"flg uf .1 4097 0\n"
|
|
"flg of .1 4098 0\n"
|
|
"flg dz .1 4099 0\n"
|
|
"flg nv .1 4100 0\n"
|
|
"flg frm .3 4101 0\n";
|
|
|
|
break;
|
|
}
|
|
return (p && *p) ? strdup(p) : NULL;
|
|
}
|
|
|
|
static int archinfo(RzAnalysis *analysis, int q) {
|
|
switch (q) {
|
|
case RZ_ANALYSIS_ARCHINFO_ALIGN:
|
|
return 4;
|
|
case RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE:
|
|
return 4;
|
|
case RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE:
|
|
if (analysis->bits == 64) {
|
|
return 4;
|
|
}
|
|
return 2;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
RzAnalysisPlugin rz_analysis_plugin_riscv_cs = {
|
|
.name = "riscv.cs",
|
|
.desc = "Capstone RISCV analyzer",
|
|
.license = "BSD",
|
|
.esil = true,
|
|
.arch = "riscv",
|
|
.get_reg_profile = get_reg_profile,
|
|
.archinfo = archinfo,
|
|
.bits = 32 | 64,
|
|
.op = &analop,
|
|
};
|
|
|
|
#ifndef RZ_PLUGIN_INCORE
|
|
RZ_API RzLibStruct rizin_plugin = {
|
|
.type = RZ_LIB_TYPE_ANALYSIS,
|
|
.data = &rz_analysis_plugin_riscv_cs,
|
|
.version = RZ_VERSION
|
|
};
|
|
#endif
|
|
|
|
#else
|
|
RzAnalysisPlugin rz_analysis_plugin_riscv_cs = { 0 };
|
|
#ifndef RZ_PLUGIN_INCORE
|
|
RZ_API RzLibStruct rizin_plugin = {
|
|
.type = RZ_LIB_TYPE_ANALYSIS,
|
|
.version = RZ_VERSION
|
|
};
|
|
#endif
|
|
#endif
|