Rot127 f40b5ef545 Hexagon v69 update (#2180) ... Also new in this commit: - Uses system registers as defined in LLVM definitions. - Several new Hexagon v69 (HVX) instructions. - File header now has the LLVM commit and timestamps of the source file generation.		2022-01-14 16:46:38 +08:00
..
6502	Add asm tests for all legal 6502 ops	2022-01-14 00:47:33 +08:00
8051
amd29k_29000_32
arc_16
arc_32
arm_16	Fix pseudo and esil of the TST instruction on ARM32 #18108 (#18110)	2020-12-30 23:20:41 -06:00
arm_32	Add test and update arm.winedbg (#18117) ##asm	2020-12-30 23:20:41 -06:00
arm_64	Fix #18619 - Wrong assembly generated for: "add x0, x0, 1, lsl #12" (ARM64) ##asm	2021-08-18 09:16:23 +02:00
arm_cortex_16
avr	Remove rX_rY Hacks in AVR ESIL (#1988)	2021-11-16 23:07:05 +01:00
bf	Change IL string syntax to s-expressions (#2193)	2022-01-11 10:08:41 +01:00
chip8
cr16
dalvik
ebc
gb	fix #16995, #16994 and some other stuff	2020-06-10 02:24:03 +02:00
h8300
hexagon	Hexagon v69 update (#2180)	2022-01-14 16:46:38 +08:00
i4004
java	Java assembler (#903)	2021-03-25 17:52:36 +08:00
lh5801
luac_5.3_16	Lua 5.3 support RzAsm + RzAnalysis	2021-04-14 16:22:15 +08:00
luac_5.4_16	Lua 5.3 support RzAsm + RzAnalysis	2021-04-14 16:22:15 +08:00
mips.gnu_64
mips_64
mips_v2_64
msp430
or1k
pic_pic18_8
riscv_32
sh
snes_16	Add asm tests for all legal 6502 ops	2022-01-14 00:47:33 +08:00
spc700	Test and Fix spc700 (#26)	2020-10-12 09:50:40 +02:00
tms320_c55x+_32
tms320_c55x_32
v810
wasm	Implement Wasm SIMD instruction disassembly (#16928)	2020-05-22 13:58:56 +02:00
x86_16	Add IL lifting testing to rz-test	2022-01-10 19:27:09 +01:00
x86_32	Implement assembler endbr32 and endbr64 instructions for x86-32/64 (#17035) ##asm	2020-06-10 19:15:46 +08:00
x86_64	Implement assembler endbr32 and endbr64 instructions for x86-32/64 (#17035) ##asm	2020-06-10 19:15:46 +08:00
z80	Fix OOB access in z80 disasm for "OP [ixy+nn]" instructions. (#17268)	2020-07-14 11:58:16 +03:00