No description
Find a file
billow 68da5f7db2
Add Renesas H8/500 plugin (#5340)
* add h8/500 plugin stub

* refactor h8500 instruction parsing and disassembly logic

* fix: remove debug print statement from h8500 EA parsing
fix: correct plugin name from h8300 to h8500
add: new test case for h8500 disassembly

* refactor: improve operand parsing and disassembly logic for h8500

* refactor: update operand representation in h8500 EA parsing

* refactor: enhance operand definitions and add test cases for h8500 instructions

* fix: add h8500 disassembly plugin to command lists

* refactor: enhance H8500 instruction and operand structures for better parsing

* refactor: update H8500 instruction set with size suffixes and enhance operand handling

* Apply suggestion from @Copilot

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

* Apply suggestion from @Copilot

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

* refactor: update H8500 operand handling and address mode definitions for consistency

* refactor: update H8500 addressing flags and operand handling for consistency

* refactor: update H8500 immediate operand syntax to use '#' prefix for consistency

* refactor: update H8500 addressing modes and mnemonics for consistency

* refactor: add new H8500 instructions BNOT, BSET, BSR, and BTST with operand handling

* refactor: update H8500 opcode definitions and add new CLR and CMP instructions

* refactor: add DADD instruction to H8500 opcode definitions and update related tests

* fix: correct memory copy size in h8500_instruction_parse function

* refactor: add DIVXU, EXTS, and EXTU instructions to H8500 opcode definitions and update tests

* refactor: add JMP instruction to H8500 opcode definitions and update tests

* refactor: add JSR instruction to H8500 opcode definitions and update tests

* refactor: add LDC, LDM, and LINK instructions to H8500 opcode definitions and update tests

* Update librz/arch/isa/h8500/h8500.c

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

* Apply suggestion from @Copilot

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

* Apply suggestion from @Copilot

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

* refactor: update H8500 addressing mode and operand flags to use ut64 type

* refactor: update H8500 addressing modes and add MOV instruction test cases

* feat: add MOVFPE, MOVTPE, and MULXU instructions to H8500 opcode and assembly

* feat: add NEG, NOT, and NOP instructions to H8500 opcode and assembly

* feat: enhance H8500 opcode with new instructions and EA flags

* fix: change enum to typedef enum for addressing mode definition

* pjmp

* pjsr | prts

* rot*

* rt*

* scb

* sh*

* sleep | stc | stm

* sub*

* swap

* tas | trapa | trap/vs | tst

* fin disas

* fix header

* add h8500_reg_name function to retrieve register names

* implement H8500 instruction analysis and operand value extraction

* refactor H8500 addressing modes and operand definitions for clarity

* fix msvc 2017 build

* fmt

* fix: update description for H8500 disassembler plugin

* fix: cmd test

* fix: coff h8500 support

* add author and cpus

* fix: test cmd

* feat: add instruction operand string retrieval and new instruction test

* fix: change operand length type from size_t to int in h8500 instruction parsing functions

* feat: add dsub instruction and update operand syntax in h8500 assembly files

* feat: update h8500 opcode descriptions and add new branch instructions

* Fix coff permissions when rz_coff_perms_from_section_flags returns 0

* Fix missing op->size

* refactor: update addressing mode macros and improve operand handling in h8500

* Refactor assembly syntax for H8500 instructions

- Added spaces for better readability in the assembly instruction definitions.
- Updated the formatting of operand lists to include spaces around commas.
- Ensured consistency in the formatting of immediate values and register references.
- Adjusted the assembly test cases to reflect the new formatting style.

* fix: correct permissions for .drectve sections in COFF format

* feat: add initial test cases for h8500 registers and analysis

* fix: add comment to clarify H8300 machine definition in COFF specs

* fix: correct typo in expected output for h8500 analysis

* fix: update data type and constants for H8500 pattern checks

* fix: apply suggestion

* fix: update H8500 instruction encoding and address modes

* fix: add cmp.b and cmp.w instructions for H8500

* fix: refactor H8500 analysis for improved address mode handling

* fix: enhance H8500 analysis for improved operand handling and stack operations

* fix: improve operand handling in H8500 analysis for better instruction processing

* fix: update PJSR instruction format for H8500 and enhance CMP instruction handling

* fix: enhance H8500 function analysis with additional metadata for varfunc and leaffunc

* fix: add documentation and clarify PC-relative mode handling in H8500 instruction parsing

* fix: correct PJMP instruction format to include address dereferencing

* Update librz/arch/isa/h8500/h8500.c

Co-authored-by: Giovanni <561184+wargio@users.noreply.github.com>

---------

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: wargio <deroad@kumo.xn--q9jyb4c>
Co-authored-by: Giovanni <561184+wargio@users.noreply.github.com>
2025-10-03 13:10:55 +00:00
.builds Run tests in OpenBSD with doas. (#5234) 2025-07-05 18:44:13 +08:00
.github Unpin meson in Windows installer builds (#5407) 2025-09-24 22:56:23 +08:00
.reuse Fix license linter 2024-03-07 18:38:49 +08:00
.woodpecker Run tests on woodpecker but be verbose. 2024-09-23 14:24:41 +08:00
binrz -h: Refactor out colored help printing code (#5421) 2025-10-01 06:02:15 +08:00
dist Drop libuv dependency 2022-08-06 13:20:52 +02:00
doc Add option to use system BLAKE3 (#5414) 2025-09-28 13:11:33 +08:00
librz Add Renesas H8/500 plugin (#5340) 2025-10-03 13:10:55 +00:00
LICENSES Move SDB into RzUtil 2022-07-19 08:45:20 +02:00
subprojects Revert -Wno-error cancel flag (#5408) 2025-09-25 20:17:06 +08:00
sys Re-format Python files according to black v25. (#4921) 2025-02-22 03:01:14 +08:00
test Add Renesas H8/500 plugin (#5340) 2025-10-03 13:10:55 +00:00
.appveyor.yml ci: install tomli for meson (#4590) 2024-08-15 20:43:00 +08:00
.clang-format refactor: Use HtSP for storing plugins. (#4687) 2024-10-26 16:31:13 +08:00
.dockerignore Drop libuv dependency 2022-08-06 13:20:52 +02:00
.gitattributes Move remaining things from shlr/ to meson subprojects (#2126) 2021-12-22 09:20:39 +08:00
.gitignore Ignore subprojects/.wraplock (#5410) 2025-09-25 20:57:27 +08:00
.lgtm.yml
.prettierignore Move remaining things from shlr/ to meson subprojects (#2126) 2021-12-22 09:20:39 +08:00
.pylintrc Redirect stderr to stdout via -1; Unbreak dk 9 test (#4664) 2024-10-12 06:37:09 +08:00
.travis.yml ci: install tomli for meson (#4590) 2024-08-15 20:43:00 +08:00
BUILDING.md Add s390x cross build example. (#5384) 2025-09-22 11:44:03 +00:00
CODE_OF_CONDUCT.md
codecov.yml String search integration tests (#5358) 2025-09-14 11:44:14 +08:00
CODEOWNERS Add myself as code owner to be added as default reviewer to PRs. (#4839) 2025-01-15 22:29:13 +08:00
CONTRIBUTING.md CONTRIBUTING.md: Remove commit hashtag requirement (#4186) 2024-02-05 18:39:37 +08:00
COPYING
COPYING.LESSER
DEVELOPERS.md util: implement iterator for hash tables and sets (#4639) 2024-09-24 21:36:54 +08:00
Dockerfile docker: update to Debian 11 (Bullseye) (#5277) 2025-07-18 12:27:28 +08:00
Doxyfile Move remaining things from shlr/ to meson subprojects (#2126) 2021-12-22 09:20:39 +08:00
meson.build Fix using system zydis (#5416) 2025-10-01 10:10:41 +08:00
meson_options.txt Add option to use system BLAKE3 (#5414) 2025-09-28 13:11:33 +08:00
README.md Update README.md (#4915) 2025-02-19 01:06:44 +08:00
SECURITY.md Update Security policy to be more precise about vulns 2021-08-25 13:13:37 +02:00
snapcraft.yaml Bump version to v0.9.0 2025-04-23 16:49:14 +08:00
travis-extract-var.sh SPDX Copyright text for all files based on history 2021-03-05 19:39:15 +08:00
travis-script Use meson setup <dir> instead of meson <dir> 2023-04-26 20:01:47 +08:00

Rizin logo

Rizin

Rizin is a reverse engineering framework, born as a fork of the radare2, with a focus on usability, features and cleanliness.

Rizin is portable and it can be used to analyze binaries, disassemble code, debug programs, as a forensic tool, as a scriptable command-line hexadecimal editor able to open disk files, and much more!

To learn more on Rizin you may want to read the official Rizin book.

How to install

Look at install instructions on our web page.

How to build

Use meson to compile and install Rizin. Please make sure to get an updated meson (e.g. get it with pip install meson if your system does not provide one that is at least version 0.55.0).

Clone this repository:

$ git clone https://github.com/rizinorg/rizin

Then compile and install with:

$ meson setup build
$ meson compile -C build
$ sudo meson install -C build

Now you can use rizin:

$ rizin
 -- Thank you for using rizin. Have a nice night!
[0x00000000]>

To uninstall rizin, execute sudo ninja -C build uninstall.

Please have a look at BUILDING.md for more information about building Rizin.

Contributing

We very much welcome any kind of contributions, from typos, to documentation, to refactoring, up to completely new features you may think of. Before contributing, we would like you to read the file CONTRIBUTING.md, so that we can all be on the same page.

Tests

Look at test/README.md.

Supported features

Supported Operating Systems

Windows 7 and higher, Apple macOS/iOS/iPadOS, GNU/Linux, [Dragonfly|Net|Free|Open]BSD, Android, QNX, Solaris/Illumos, Haiku, GNU/Darwin, GNU/Hurd.

Supported Architectures

i386, x86-64, ARM/ARM64, RISC-V, PowerPC, MIPS, AVR, SPARC, System Z (S390), SuperH, m68k, m680x, XAP, XCore, CR16, HPPA, ARC, Blackfin, Z80, H8/300, Renesas (V810, V850, RL78), CRIS, XAP, PIC, LM32, 8051, 6502, i4004, i8080, Propeller, Tricore, CHIP-8, LH5801, T8200, GameBoy, SNES, SPC700, MSP430, Xtensa, NIOS II, TMS320 (c54x, c55x, c55+, c64x), Hexagon, DCPU16, LANAI, MCORE, mcs96, RSP, C-SKY(MCore), VAX, AMD Am29000.

There is also support for the following bytecode formats:

Dalvik, EBC, Java, Lua, Python, WebAssembly, Brainfuck, Malbolge

Supported File Formats

ELF, Mach-O, Fatmach-O, PE, PE+, MZ, COFF, OMF, NE, LE, LX, TE, XBE, BIOS/UEFI, Dyldcache, DEX, ART, CGC, ELF, Java class, Android boot image, Plan9 executable, ZIMG, MBN/SBL bootloader, ELF coredump, MDMP (Windows minidump), DMP (Windows pagedump), WASM (WebAssembly binary), Commodore VICE emulator, QNX, Game Boy (Advance), Nintendo DS ROMs and Nintendo 3DS FIRMs.

Tools

Apart from the main tool rizin, there are also other tools tailored for specific purposes and useful for shell scripting or as separate standalone tools:

  • rz-bin - provides all kind of information about binary formats
  • rz-asm - a command-line assembler and disassemblers
  • rz-diff - a tool to compare two binaries as raw data or analyzed executables
  • rz-hash - allows to calculate different hashes or even encrypt data
  • rz-gg - a small "eggs" code generator useful for exploitation purposes
  • rz-find - binary analog of find tool, allowing to search patterns and bit masks
  • rz-sign - tool to create, convert and parse FLIRT signatures
  • rz-ax - a calculator and number format converter
  • rz-run - a tool that allows to specify running environment and arguments for debugged file

Scripting

We provide a way to interact with Rizin from Python, Haskell, OCaml, Ruby, Rust, and Go languages through rzpipe. Other languages although not currently supported could be easily added.

Community

Our website and blog: https://www.rizin.re/

Join our Mattermost community to discuss Rizin, its development, and general topics related to the project.

We also provide the following partial bridges to other messaging platforms: