3c2e4bf63a
* Show group-level details of commands Details can be defined at either a group command or its subcommand of the same name. If define on group-level it will also be shown in the group help without needing ??. * Fix > $ redirection for errored command and leak * Rewrite ar and dr commands with newshell Breaking changes: ar* => arf, ar- => arf-, ar. => ar* ar, => art, ar? => arq ar0 => ara0, arb => arab, ars => araS arC => arpC arn => arR art => arT arf => arF Removed: drm, aer
106 lines
892 B
Text
106 lines
892 B
Text
NAME=ara swap
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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ara+
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ar rax=33
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ar rax
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aras
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ar rax
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EOF
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EXPECT=<<EOF
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rax = 0x00000021
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rax = 0x00000000
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EOF
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RUN
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NAME=ara swap 2
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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ara+
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ar rax=33
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ar rax
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aras
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ar rax
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aras
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ar rax
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EOF
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EXPECT=<<EOF
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rax = 0x00000021
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rax = 0x00000000
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rax = 0x00000021
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EOF
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RUN
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NAME=ara push
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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ara~?
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ara+
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ara~?
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EOF
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EXPECT=<<EOF
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20
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30
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EOF
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RUN
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NAME=ara pop
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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ara~?
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ara+
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ara~?
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ara-
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ara~?
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ara-
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ara~?
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ara-
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ara~?
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EOF
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EXPECT=<<EOF
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20
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30
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20
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10
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10
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EOF
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RUN
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NAME=arcc+tcc
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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afcl
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e asm.arch=arm
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e asm.bits=32
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arcc
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e asm.arch=x86
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e asm.bits=64
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arcc
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tcc `arcc`
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afcl
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EOF
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EXPECT=<<EOF
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amd64
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amd64syscall
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ms
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reg
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swift
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r0 reg(r0, r1, r2, r3)
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rdi reg(rdi, rsi, rdx, rcx)
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amd64
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amd64syscall
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ms
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reg
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swift
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EOF
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RUN
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