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rizin/test/db/esil/arm_16
Giovanni 70fdd67278
Allow rizin tools to run as standalone binaries (#6011) 
* Implement TOOL/ENVS/EXIT_STATUS for rz-test

* update readme
2026-03-11 16:24:23 +00:00

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NAME=adr emulation
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
e io.cache=true
s 0x0008735c
wx 30a1
w rizin_emulation\x00 @ 0x87420
aei
aeim
aeip
aes
ps @ r1
EOF
EXPECT=<<EOF
rizin_emulation
EOF
RUN
NAME=clz
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wa "clz r0, r1"
ar r1=0x80000000
aes
ar r0
ara0
ar r1=0x1
aes
ar r0
ara0
aes
ar r0
EOF
EXPECT=<<EOF
r0 = 0x00000000
r0 = 0x0000001f
r0 = 0x00000020
EOF
RUN
NAME=addw emulation
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
e io.cache=true
s 0x00088a1c
wx 0ff26c71
w addw_emulation\x00 @ 0x8918c
aei
aeim
aeip
aes
ps @ r1
EOF
EXPECT=<<EOF
addw_emulation
EOF
RUN
NAME=cmp neq unchanged zf
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
aei
aeim
ar sp=0x00108000
.arf
wa "cmp r1, 16"
aes
%v cpsr & 0xf0000000
EOF
EXPECT=<<EOF
0x80000000
EOF
RUN
NAME=cmp neq changed zf
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
aei
aeim
ar sp=0x00108000
ar cpsr=0xffffffff
.arf
wa "cmp r1, 16"
aes
%v cpsr & 0xf0000000
EOF
EXPECT=<<EOF
0x80000000
EOF
RUN
NAME=cmp eq unchanged zf
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
aei
aeim
ar sp=0x00108000
ar r1=0x10
ar cpsr=0x40000000
.arf
wa "cmp r1, 16"
aes
%v cpsr & 0xf0000000
EOF
EXPECT=<<EOF
0x60000000
EOF
RUN
NAME=cmp eq changed zf
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
aei
aeim
ar sp=0x00108000
ar r1=0x10
ar cpsr=0x00000000
.arf
wa "cmp r1, 16"
aes
%v cpsr & 0xf0000000
EOF
EXPECT=<<EOF
0x60000000
EOF
RUN
NAME=ldr.w r0, [r0, r1, lsl 2]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar > /dev/null
ar r0=4
ar r1=2
wx 50f82100
wx aaaaaaaabbbbbbbb44332211@ 4
aes
ar r0
EOF
EXPECT=<<EOF
r0 = 0x11223344
EOF
RUN
NAME=ldrd r2, r3, [r1]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar r1=8
# put value at r1 into r2 and at r1+4 into r3
wx d1e90023 # ldrd r2,r3,[r1]
wx ddccbbaa @ 8
wx efbeadde @ 12
aes
ar r2
ar r3
EOF
EXPECT=<<EOF
r2 = 0xaabbccdd
r3 = 0xdeadbeef
EOF
RUN
NAME=ldrd r2, r3, [r1, #4]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar r1=4
# put value at r1+4 into r2 and at r1+4+4 into r3
wx d1e90123 # ldrd r2,r3,[r1, 4]
wx ddccbbaa @ 8
wx efbeadde @ 12
aes
ar r2
ar r3
EOF
EXPECT=<<EOF
r2 = 0xaabbccdd
r3 = 0xdeadbeef
EOF
RUN
NAME=ldrd r2, r3, [pc, #8]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
# put value at pc+4 into r2 and at pc+4+4 into r3
wx dfe90223 # ldrd r2, r3, [pc, #8]
wx ddccbbaa @ 12
wx efbeadde @ 16
aes
ar r2
ar r3
EOF
EXPECT=<<EOF
r2 = 0xaabbccdd
r3 = 0xdeadbeef
EOF
RUN
NAME=ldrd r2, r3, [r1, #4]!
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar r1=4
# put value at r1+4 into r2 and at r1+4+4 into r3 then put r1+4 into r1
wx f1e90123 # ldrd r2, r3, [r1, #4]!
wx ddccbbaa @ 8
wx efbeadde @ 12
aes
ar r1
ar r2
ar r3
EOF
EXPECT=<<EOF
r1 = 0x00000008
r2 = 0xaabbccdd
r3 = 0xdeadbeef
EOF
RUN
NAME=ldrd r2, r3, [r1], #4
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar r1=8
# put value at r1 into r2 and at r1+4 into r3 then put r1+4 into r1
wx f1e80123 # ldrd r2,r3,[r1], 4
wx ddccbbaa @ 8
wx efbeadde @ 12
aes
ar r1
ar r2
ar r3
EOF
EXPECT=<<EOF
r1 = 0x0000000c
r2 = 0xaabbccdd
r3 = 0xdeadbeef
EOF
RUN
NAME=ldm r3!, {r1, r4, r5}
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar > /dev/null
ar r3=4 # address
ar r1=0 # init with dummy values
ar r4=0
ar r5=0
wx 32cb
wx 111111114444444455555555@ 4
aes
ar r1; ar r4; ar r5; ar r3
EOF
EXPECT=<<EOF
r1 = 0x11111111
r4 = 0x44444444
r5 = 0x55555555
r3 = 0x00000010
EOF
RUN
NAME=stm r1!, {r5}
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar r1=4 # address
ar r5=0xaabbccdd
wx 20c1
aes
ar r1
p8 4 @ 4
EOF
EXPECT=<<EOF
r1 = 0x00000008
ddccbbaa
EOF
RUN
NAME=stm r2!, {r1, r4, r5}
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar > /dev/null
ar r2=4 # address
ar r1=0x11111111
ar r4=0x44444444
ar r5=0x55555555
wx 32c2
aes
pfv x @ 4; pfv x @ 8; pfv x @ 12; ar r2
EOF
EXPECT=<<EOF
0x11111111
0x44444444
0x55555555
r2 = 0x00000010
EOF
RUN
NAME=ubfx r2, r0, 8, 8
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar > /dev/null
ar r0=0x11223344
wx c0f30722
aes
ar r2
EOF
EXPECT=<<EOF
r2 = 0x00000033
EOF
RUN
NAME=it eq
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 08bf
aoe
EOF
EXPECT=<<EOF
0x0 zf,?{,2,$$,+,pc,=,}
EOF
RUN
NAME=it ne
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 18bf00000000
aoe
EOF
EXPECT=<<EOF
0x0 zf,!,?{,2,$$,+,pc,=,}
EOF
RUN
NAME=it hs
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 28bf00000000
aoe
EOF
EXPECT=<<EOF
0x0 cf,?{,2,$$,+,pc,=,}
EOF
RUN
NAME=it lo
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 38bf00000000
aoe
EOF
EXPECT=<<EOF
0x0 cf,!,?{,2,$$,+,pc,=,}
EOF
RUN
NAME=it mi
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 48bf00000000
aoe
EOF
EXPECT=<<EOF
0x0 nf,?{,2,$$,+,pc,=,}
EOF
RUN
NAME=it pl
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 58bf00000000
aoe
EOF
EXPECT=<<EOF
0x0 nf,!,?{,2,$$,+,pc,=,}
EOF
RUN
NAME=it vs
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 68bf00000000
aoe
EOF
EXPECT=<<EOF
0x0 vf,?{,2,$$,+,pc,=,}
EOF
RUN
NAME=it vc
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 78bf00000000
aoe
EOF
EXPECT=<<EOF
0x0 vf,!,?{,2,$$,+,pc,=,}
EOF
RUN
NAME=it al
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx e8bf00000000
aoe
EOF
EXPECT=<<EOF
0x0 2,$$,+,pc,=
EOF
RUN
NAME=ldr r2, [r3, r1]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar r3=1
ar r1=2
wx 5a58aabbccddeeff
aes
ar r2
EOF
EXPECT=<<EOF
r2 = 0xeeddccbb
EOF
RUN
NAME=lsls r1, r2
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar > /dev/null
ar r1=0x80000001
ar r2=0x1
wa "lsls r1, r2;lsls r1, r2"
aes
ar r1
ar cpsr
aes
ar r1
ar cpsr
EOF
EXPECT=<<EOF
r1 = 0x00000002
cpsr = 0x20000000
r1 = 0x00000004
cpsr = 0x00000000
EOF
RUN
NAME=lsrs r1, r2
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar > /dev/null
ar r1=-8
ar r2=2
wa "lsrs r1, r2;lsrs r1, r2"
aes
ar r1
ar cpsr
aes
ar r1
ar cpsr
EOF
EXPECT=<<EOF
r1 = 0x3ffffffe
cpsr = 0x00000000
r1 = 0x0fffffff
cpsr = 0x20000000
EOF
RUN
NAME=asrs r4, r4, 2
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar > /dev/null
ar r4=-8
wx a410
aes
ar r4
EOF
EXPECT=<<EOF
r4 = 0xfffffffe
EOF
RUN
NAME=orn
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar r1=0x3
ar r2=0x7
wv 0x0002ea61
aes
ar r0
EOF
EXPECT=<<EOF
r0 = 0xfffffffb
EOF
RUN
NAME=add pc
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wv 0x4478
aes
ar r0
EOF
EXPECT=<<EOF
r0 = 0x00000004
EOF
RUN
NAME=ldm.w r0, {r4, r6}
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 90e85000
wv 0x11223344 @ 4
wv 0x55667788 @ 8
ar r0=4
aes
ar r4
ar r6
EOF
EXPECT=<<EOF
r4 = 0x11223344
r6 = 0x55667788
EOF
RUN
NAME=ldr wrapping around addresses
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 7158 #ldr r1, [r6, r1]
wv 0x11223344 @ 2
ar r1=0x4796eebe
ar r6=0xb8691144
aes
ar r1
EOF
EXPECT=<<EOF
r1 = 0x11223344
EOF
RUN
NAME=ldr immediate with post increment
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wa "ldr r2, [r3], 10"
wx aabbccdd @ 10
ar r3=10
aes
ar r2
ar r3
EOF
EXPECT=<<EOF
r2 = 0xddccbbaa
r3 = 0x00000014
EOF
RUN
NAME=add wrapping around
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 0144 #add r1, r0
ar r1=0x4796eebe
ar r0=0xb8691144
aes
ar r1
EOF
EXPECT=<<EOF
r1 = 0x00000002
EOF
RUN
NAME=adcs wrapping around
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wa "adcs r1, r3;adcs r1, r3"
ar r1=0x90000000
ar r3=0x80000000
ar cpsr=0x00000000
aes
ar r1
ar cpsr
aes
ar r1
ar cpsr
EOF
EXPECT=<<EOF
r1 = 0x10000000
cpsr = 0x30000000
r1 = 0x90000001
cpsr = 0x80000000
EOF
RUN
NAME=adds with carry and zero
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wa "adds r1, 1"
ar r1=0xffffffff
aes
ar r1
ar cpsr
EOF
EXPECT=<<EOF
r1 = 0x00000000
cpsr = 0x60000000
EOF
RUN
NAME=subs with carry and zero
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wa "subs r1, 1"
ar r1=1
aes
ar r1
ar cpsr
EOF
EXPECT=<<EOF
r1 = 0x00000000
cpsr = 0x60000000
EOF
RUN
NAME=smmla
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 51fb0001 #smmla r1, r1, r0, r0
ar r1=0x4796eebe
ar r0=0x11
aes
ar r1
EOF
EXPECT=<<EOF
r1 = 0x00000015
EOF
RUN
NAME=smmlar
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 51fb1001 #smmlar r1, r1, r0, r0
ar r1=0x4796eebe
ar r0=0x11
aes
ar r1
EOF
EXPECT=<<EOF
r1 = 0x00000016
EOF
RUN
NAME=umull
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx a1fb0212 #umull r1, r2, r1, r2
ar r1=0x4796eebe
ar r2=0x11
aes
ar r1
ar r2
EOF
EXPECT=<<EOF
r1 = 0xc105da9e
r2 = 0x00000004
EOF
RUN
NAME=mls
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 01fb1200 #mls r0, r1, r2, r0
ar r0=0x16161616
ar r1=0x45
ar r2=0x7823834
aes
ar r0
EOF
EXPECT=<<EOF
r0 = 0x0ffcf012
EOF
RUN
NAME=mla
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 00fb0211 #mla r1, r0, r2, r1
ar r1=0x16161616
ar r0=0x45
ar r2=0x7823834
aes
ar r1
EOF
EXPECT=<<EOF
r1 = 0x1c2f3c1a
EOF
RUN
NAME=mvn
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 6ff01201 #mvn r1, 0x12
aes
ar r1
EOF
EXPECT=<<EOF
r1 = 0xffffffed
EOF
RUN
NAME=bfc
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar r4=0x696969f9
wx 6ff30604 #bfc r4, 0, 7
aes
ar r4
EOF
EXPECT=<<EOF
r4 = 0x69696980
EOF
RUN
NAME=bfi
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar r2=0x696969f9
ar r3=0x33333333
wx 62f38703 #bfi r3, r2, 2, 6
aes
ar r3
EOF
EXPECT=<<EOF
r3 = 0x333333e7
EOF
RUN
NAME=rev
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar r5=0x11223344
wx 2bba #rev r3, r5
aes
ar r3
EOF
EXPECT=<<EOF
r3 = 0x44332211
EOF
RUN
NAME=rev16
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar r7=0x11223344
wx 7eba #rev16 r6, r7
aes
ar r6
EOF
EXPECT=<<EOF
r6 = 0x22114433
EOF
RUN
NAME=revsh positive
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar r1=0x11223344
wx cfba #revsh r7, r1
aes
ar r7
EOF
EXPECT=<<EOF
r7 = 0x00004433
EOF
RUN
NAME=revsh negative
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
ar r1=0x11223388
wx cfba #revsh r7, r1
aes
ar r7
EOF
EXPECT=<<EOF
r7 = 0xffff8833
EOF
RUN
NAME=cbz/cbnz likeliness
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bytes=true
e asm.bits=16
e cfg.bigendian=false
e emu.str=true
wv2 0x2000
wv2 0x2101 @ 2
wv2 0xb100 @ 4
wv2 0xbf00 @ 6
wv2 0x2000 @ 8
wv2 0x2101 @ 10
wv2 0xb900 @ 12
pd 7
EOF
EXPECT=<<EOF
0x00000000 0020 movs r0, 0
0x00000002 0121 movs r1, 1
,=< 0x00000004 00b1 cbz r0, 8 ; likely
| 0x00000006 00bf nop
`-> 0x00000008 0020 movs r0, 0
0x0000000a 0121 movs r1, 1
,=< 0x0000000c 00b9 cbnz r0, 0x10 ; unlikely
EOF
RUN
NAME=pc points to next instruction
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 7846 # mov r0, pc
aes
ar r0
EOF
EXPECT=<<EOF
r0 = 0x00000002
EOF
RUN
NAME=lr correct after bl
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 00f002f8 # bl 8
aes
ar lr
ar pc
EOF
EXPECT=<<EOF
lr = 0x00000005
pc = 0x00000008
EOF
RUN
NAME=arm s110 syscalls /ad svc
FILE=bins/elf/BLE_Beacon2.NRF51822_OTA.bin
ARGS=-m 0x16000
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e asm.os=s110
e cfg.bigendian=false
/ad svc
EOF
EXPECT=<<EOF
0x000168d0 # 2: svc 0x51
0x000168f2 # 2: svc 0x61
0x00016b42 # 2: svc 0x7f
0x00016c1c # 2: svc 0x7c
0x00016c28 # 2: svc 0x78
0x00016c32 # 2: svc 0x7a
0x00016c3a # 2: svc 0x77
0x00016ce4 # 2: svc 0xa0
0x00016ed6 # 2: svc 0xa9
0x000171b2 # 2: svc 0x73
0x00017212 # 2: svc 0x72
0x0001721e # 2: svc 0x78
0x00017408 # 2: svc 0x40
0x000177f6 # 2: svc 0x3c
0x000177f8 # 2: svc 0x11
0x00017820 # 2: svc 0x13
0x0001785c # 2: svc 0x60
0x00017864 # 2: svc 0x71
0x0001786c # 2: svc 0x70
0x0001794c # 2: svc 0xa2
0x0001799e # 2: svc 0xa3
0x00017a1a # 2: svc 0x63
0x00017d5e # 2: svc 0x10
0x00017d6a # 2: svc 0x26
0x00018660 # 2: svc 0xa4
EOF
RUN
NAME=Pre-indexed addressing mode
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wx 10f8013f # ldrb r3, [r0, 1]!
aes
ar pc
ar r0
ar r3
EOF
EXPECT=<<EOF
pc = 0x00000004
r0 = 0x00000001
r3 = 0x000000f8
EOF
RUN
NAME=test-thumb-load
FILE=malloc://0x200
CMDS=<<EOF
e asm.bytes=true
e asm.arch=arm
e asm.bits=16
e cfg.bigendian=false
wb 054b
pd 10
EOF
EXPECT=<<EOF
0x00000000 054b ldr r3, [0x00000018] ; [0x18:4]=0x4b054b05
0x00000002 054b ldr r3, [0x00000018] ; [0x18:4]=0x4b054b05
0x00000004 054b ldr r3, [0x0000001c] ; [0x1c:4]=0x4b054b05
0x00000006 054b ldr r3, [0x0000001c] ; [0x1c:4]=0x4b054b05
0x00000008 054b ldr r3, [0x00000020] ; [0x20:4]=0x4b054b05
0x0000000a 054b ldr r3, [0x00000020] ; [0x20:4]=0x4b054b05
0x0000000c 054b ldr r3, [0x00000024] ; [0x24:4]=0x4b054b05
0x0000000e 054b ldr r3, [0x00000024] ; [0x24:4]=0x4b054b05
0x00000010 054b ldr r3, [0x00000028] ; [0x28:4]=0x4b054b05
0x00000012 054b ldr r3, [0x00000028] ; [0x28:4]=0x4b054b05
EOF
RUN
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