7a77b8f7bd
* fix: format with clang-format-20 * fix: fix clang-format linter with rewrite '^#define.*/\*.*\\$' * fix: update clang-format to version 20 in workflows and documentation * fix: add SPDX license information to .git-blame-ignore-revs
149 lines
3.1 KiB
C
149 lines
3.1 KiB
C
// SPDX-FileCopyrightText: 2015 danielps
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// SPDX-License-Identifier: LGPL-3.0-only
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#ifndef RZ_V810_DISASM_H
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#define RZ_V810_DISASM_H
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#define V810_INSTR_MAXLEN 24
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#define OPCODE(instr) (((instr) >> 10) & 0x3F)
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#define REG1(instr) ((instr) & 0x1F)
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#define REG2(instr) (((instr) >> 5) & 0x1F)
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#define IMM5(instr) REG1((instr))
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#define COND(instr) (((instr) >> 9) & 0xF)
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#define SIGN_EXT_T5(imm) (((imm) & 0x10) ? (imm) | 0xE0 : (imm))
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#define SIGN_EXT_T9(imm) (((imm) & 0x100) ? (imm) | 0xFFFFFE00 : (imm))
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#define SIGN_EXT_T26(imm) (((imm) & 0x2000000) ? (imm) | 0xFC000000 : (imm))
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#define DISP9(word1) SIGN_EXT_T9((word1) & 0x1FE)
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#define DISP26(word1, word2) SIGN_EXT_T26((((word1) & 0x3FF) << 16) | (word2))
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enum v810_cmd_opcodes {
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V810_MOV = 0x0,
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V810_ADD = 0x1,
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V810_SUB = 0x2,
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V810_CMP = 0x3,
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V810_SHL = 0x4,
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V810_SHR = 0x5,
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V810_JMP = 0x6,
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V810_SAR = 0x7,
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V810_MUL = 0x8,
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V810_DIV = 0x9,
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V810_MULU = 0xA,
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V810_DIVU = 0xB,
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V810_OR = 0xC,
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V810_AND = 0xD,
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V810_XOR = 0xE,
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V810_NOT = 0xF,
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V810_MOV_IMM5 = 0x10,
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V810_ADD_IMM5 = 0x11,
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V810_SETF = 0x12,
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V810_CMP_IMM5 = 0x13,
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V810_SHL_IMM5 = 0x14,
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V810_SHR_IMM5 = 0x15,
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V810_CLI = 0x16,
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V810_SAR_IMM5 = 0x17,
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V810_TRAP = 0x18,
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V810_RETI = 0x19,
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V810_HALT = 0x1A,
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V810_LDSR = 0x1C,
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V810_STSR = 0x1D,
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V810_SEI = 0x1E,
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V810_BSTR = 0x1F,
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V810_BCOND = 0x20,
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V810_MOVEA = 0x28,
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V810_ADDI = 0x29,
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V810_JR = 0x2A,
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V810_JAL = 0x2B,
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V810_ORI = 0x2C,
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V810_ANDI = 0x2D,
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V810_XORI = 0x2E,
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V810_MOVHI = 0x2F,
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V810_LDB = 0x30,
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V810_LDH = 0x31,
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V810_LDW = 0x33,
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V810_STB = 0x34,
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V810_STH = 0x35,
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V810_STW = 0x37,
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V810_INB = 0x38,
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V810_INH = 0x39,
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V810_CAXI = 0x3A,
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V810_INW = 0x3B,
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V810_OUTB = 0x3C,
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V810_OUTH = 0x3D,
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V810_EXT = 0x3E,
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V810_OUTW = 0x3F,
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};
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enum v810_bit_ops {
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V810_BIT_SCH0U = 0x0,
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V810_BIT_SCH0D = 0x1,
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V810_BIT_SCH1U = 0x2,
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V810_BIT_SCH1D = 0x3,
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V810_BIT_ORU = 0x8,
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V810_BIT_ANDU = 0x9,
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V810_BIT_XORU = 0xA,
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V810_BIT_MOVU = 0xB,
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V810_BIT_ORNU = 0xC,
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V810_BIT_ANDNU = 0xD,
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V810_BIT_XORNU = 0xE,
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V810_BIT_NOTU = 0xF,
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};
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enum v810_ext_ops {
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V810_EXT_CMPF_S = 0x0,
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V810_EXT_CVT_WS = 0x2,
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V810_EXT_CVT_SW = 0x3,
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V810_EXT_ADDF_S = 0x4,
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V810_EXT_SUBF_S = 0x5,
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V810_EXT_MULF_S = 0x6,
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V810_EXT_DIVF_S = 0x7,
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V810_EXT_XB = 0x8,
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V810_EXT_XH = 0x9,
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V810_EXT_REV = 0xA,
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V810_EXT_TRNC_SW = 0xB,
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V810_EXT_MPYHW = 0xC,
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};
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enum v810_conds {
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V810_COND_V = 0x0,
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V810_COND_L = 0x1,
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V810_COND_E = 0x2,
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V810_COND_NH = 0x3,
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V810_COND_N = 0x4,
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V810_COND_NONE = 0x5,
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V810_COND_LT = 0x6,
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V810_COND_LE = 0x7,
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V810_COND_NV = 0x8,
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V810_COND_NL = 0x9,
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V810_COND_NE = 0xA,
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V810_COND_H = 0xB,
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V810_COND_P = 0xC,
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V810_COND_NOP = 0xD,
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V810_COND_GE = 0xE,
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V810_COND_GT = 0xF,
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};
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enum v810_sysregs {
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V810_SREG_EIPC = 0x0,
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V810_SREG_EIPSW = 0x1,
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V810_SREG_FEPC = 0x2,
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V810_SREG_FEPSW = 0x3,
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V810_SREG_ECR = 0x4,
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V810_SREG_PSW = 0x5,
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V810_SREG_PIR = 0x6,
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V810_SREG_TKCW = 0x7,
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V810_SREG_CHCW = 0x18,
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V810_SREG_ADTRE = 0x19,
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};
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struct v810_cmd {
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unsigned type;
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char instr[V810_INSTR_MAXLEN];
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char operands[V810_INSTR_MAXLEN];
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};
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int v810_decode_command(const ut8 *instr, int len, struct v810_cmd *cmd);
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#endif /* RZ_V810_DISASM_H */
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