246 lines
11 KiB
C
246 lines
11 KiB
C
// SPDX-FileCopyrightText: 2021 GustavoLCR <gugulcr@gmail.com>
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// SPDX-License-Identifier: LGPL-3.0-only
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#include <rz_analysis.h>
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#include <rz_core.h>
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#include "minunit.h"
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#define SWITCH_TO_ARCH_BITS(arch, bits) \
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rz_analysis_use(analysis, arch); \
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rz_analysis_set_bits(analysis, bits);
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bool test_rz_analysis_op_val() {
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RzAnalysis *analysis = rz_analysis_new(NULL);
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RzAnalysisOp op;
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SWITCH_TO_ARCH_BITS("x86", 64);
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// mov rax, [rbx+rcx+4]
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rz_analysis_op_init(&op);
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int len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\x48\x8b\x44\x0b\x04", 5, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 5, "Op is of size 5");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_REG, "Destination should be reg");
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mu_assert_streq(op.dst->reg->name, "rax", "Dst reg should be rax");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_MEM, "Source should be mem");
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mu_assert_streq(op.src[0]->reg->name, "rbx", "Source reg base should be rbx");
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mu_assert_streq(op.src[0]->regdelta->name, "rcx", "Source reg delta should be rcx");
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mu_assert_eq(op.src[0]->delta, 4, "Source delta should be 4");
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rz_analysis_op_fini(&op);
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rz_analysis_op_init(&op);
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len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\x48\xc7\xc0\x04\x00\x00\x00", 7, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 7, "Op is of size 7");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_REG, "Destination should be reg");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_IMM, "Source should be imm");
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mu_assert_eq(op.src[0]->imm, 4, "Source imm should be 4");
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rz_analysis_op_fini(&op);
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SWITCH_TO_ARCH_BITS("arm", 64);
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// ldr x1, [x2, x3]
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rz_analysis_op_init(&op);
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len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\x41\x68\x63\xf8", 4, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 4, "Op is of size 4");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_REG, "Destination should be reg");
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mu_assert_streq(op.dst->reg->name, "x1", "Dst reg should be x1");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_MEM, "Source should be mem");
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mu_assert_streq(op.src[0]->reg->name, "x2", "Source reg base should be x2");
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mu_assert_streq(op.src[0]->regdelta->name, "x3", "Source reg base should be x3");
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rz_analysis_op_fini(&op);
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// mov x1, 400
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rz_analysis_op_init(&op);
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len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\x01\x32\x80\xd2", 4, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 4, "Op is of size 4");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_REG, "Destination should be reg");
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mu_assert_streq(op.dst->reg->name, "x1", "Dst reg should be x1");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_IMM, "Source should be imm");
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mu_assert_eq(op.src[0]->imm, 400, "Source imm should be 400");
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rz_analysis_op_fini(&op);
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SWITCH_TO_ARCH_BITS("arm", 32);
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// ldr r1, [ r2, r3 ]
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rz_analysis_op_init(&op);
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len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\x03\x10\x92\xe7", 4, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 4, "Op is of size 4");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_REG, "Destination should be reg");
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mu_assert_streq(op.dst->reg->name, "r1", "Dst reg should be r1");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_MEM, "Source should be mem");
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mu_assert_streq(op.src[0]->reg->name, "r2", "Source reg base should be r2");
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mu_assert_streq(op.src[0]->regdelta->name, "r3", "Source reg base should be r3");
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rz_analysis_op_fini(&op);
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SWITCH_TO_ARCH_BITS("arm", 16);
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// ldr r1, [ r2, r3 ]
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rz_analysis_op_init(&op);
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len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\xd1\x58", 2, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 2, "Op is of size 2");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_REG, "Destination should be reg");
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mu_assert_streq(op.dst->reg->name, "r1", "Dst reg should be r1");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_MEM, "Source should be mem");
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mu_assert_streq(op.src[0]->reg->name, "r2", "Source reg base should be r2");
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mu_assert_streq(op.src[0]->regdelta->name, "r3", "Source reg base should be r3");
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rz_analysis_op_fini(&op);
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SWITCH_TO_ARCH_BITS("riscv", 32);
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rz_analysis_set_cpu(analysis, "rv32i2p0_c2p0");
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// lw s10, 64(sp)
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rz_analysis_op_init(&op);
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len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\x06\x4d", 2, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 2, "Op is of size 2");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_REG, "Destination should be reg");
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mu_assert_streq(op.dst->reg->name, "s10", "Dst reg should be s10");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_MEM, "Source should be mem");
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mu_assert_streq(op.src[0]->reg->name, "sp", "Source reg base should be sp");
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mu_assert_eq(op.src[0]->delta, 64, "Source delta should be 64");
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rz_analysis_op_fini(&op);
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// sw s0, 136(sp)
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rz_analysis_op_init(&op);
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len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\x22\xc5", 2, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 2, "Op is of size 2");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_MEM, "Destination should be mem");
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mu_assert_streq(op.dst->reg->name, "sp", "Dst reg should be s10");
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mu_assert_eq(op.dst->delta, 136, "Source delta should be 64");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_REG, "Source should be reg");
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mu_assert_streq(op.src[0]->reg->name, "s0", "Source reg base should be s0");
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rz_analysis_op_fini(&op);
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rz_analysis_free(analysis);
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mu_end;
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}
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bool test_rz_core_analysis_bytes() {
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RzCore *core = rz_core_new();
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rz_core_arch_configure(core, "x86", 64, NULL, NULL, NULL);
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ut8 buf[128];
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int len = rz_hex_str2bin("554889e5897dfc", buf);
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RzIterator *iter = rz_core_analysis_bytes(core, core->offset, buf, len, 0);
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mu_assert_notnull(iter, "rz_core_analysis_bytes");
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RzAnalysisBytes *ab = rz_iterator_next(iter);
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mu_assert_streq(ab->opcode, "push rbp", "rz_core_analysis_bytes opcode");
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free(ab->pseudo);
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ab = rz_iterator_next(iter);
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mu_assert_streq(ab->opcode, "mov rbp, rsp", "rz_core_analysis_bytes opcode");
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mu_assert_streq(ab->pseudo, "rbp = rsp", "rz_core_analysis_bytes pseudo");
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free(ab->pseudo);
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ab = rz_iterator_next(iter);
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mu_assert_streq(ab->opcode, "mov dword [rbp-0x04], edi", "rz_core_analysis_bytes opcode");
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mu_assert_streq(ab->pseudo, "dword [rbp-0x04] = edi", "rz_core_analysis_bytes pseudo");
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free(ab->pseudo);
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rz_iterator_free(iter);
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rz_core_free(core);
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mu_end;
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}
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bool test_rz_core_print_disasm() {
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RzCore *core = rz_core_new();
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rz_io_open_at(core->io, "malloc://0x100", RZ_PERM_RX, 0644, 0, NULL); // needed to get arrow info (is_valid_offset checks)
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rz_core_arch_configure(core, "x86", 64, NULL, NULL, NULL);
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rz_config_set_b(core->config, "asm.lines", false); // arrow info in struct, but not in textual disasm
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ut8 buf[128];
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int len = rz_hex_str2bin("554889e5897dfcebf8", buf);
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RzPVector *vec = rz_pvector_new((RzPVectorFree)rz_analysis_disasm_text_free);
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RzCoreDisasmOptions options = {
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.vec = vec,
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.cbytes = 1,
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};
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mu_assert_notnull(vec, "rz_core_print_disasm vec not null");
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rz_core_print_disasm(core, 0, buf, len, len, NULL, &options);
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mu_assert_eq(rz_pvector_len(vec), 4, "rz_core_print_disasm len");
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RzAnalysisDisasmText *t = rz_pvector_at(vec, 0);
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mu_assert_eq(t->offset, 0, "rz_core_print_disasm offset");
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mu_assert_eq(t->arrow, UT64_MAX, "rz_core_print_disasm arrow");
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mu_assert_streq_free(rz_str_trim_dup(t->text),
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"\x1b[32m\x1b[7m0x00000000\x1b[0m \x1b[35mpush\x1b[0m\x1b[37m \x1b[0m\x1b[36mrbp\x1b[0m\x1b[0m\x1b[0m",
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"rz_core_print_disasm text");
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t = rz_pvector_at(vec, 1);
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mu_assert_eq(t->offset, 1, "rz_core_print_disasm offset");
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mu_assert_eq(t->arrow, UT64_MAX, "rz_core_print_disasm arrow");
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mu_assert_streq_free(rz_str_trim_dup(t->text),
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"\x1b[32m0x00000001\x1b[0m \x1b[37mmov\x1b[0m\x1b[37m \x1b[0m\x1b[36mrbp\x1b[0m\x1b[37m, \x1b[0m\x1b[36mrsp\x1b[0m\x1b[0m\x1b[0m",
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"rz_core_print_disasm text");
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t = rz_pvector_at(vec, 2);
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mu_assert_eq(t->offset, 4, "rz_core_print_disasm offset");
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mu_assert_eq(t->arrow, UT64_MAX, "rz_core_print_disasm arrow");
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mu_assert_streq_free(rz_str_trim_dup(t->text),
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"\x1b[32m0x00000004\x1b[0m \x1b[37mmov\x1b[0m\x1b[37m \x1b[0m\x1b[37mdword\x1b[0m\x1b[37m [\x1b[0m\x1b[36mrbp\x1b[0m\x1b[37m-\x1b[0m\x1b[33m0x04\x1b[0m\x1b[37m], \x1b[0m\x1b[36medi\x1b[0m\x1b[0m\x1b[0m",
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"rz_core_print_disasm text");
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t = rz_pvector_at(vec, 3);
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mu_assert_eq(t->offset, 7, "rz_core_print_disasm offset");
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mu_assert_eq(t->arrow, 1, "rz_core_print_disasm arrow");
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mu_assert_streq_free(rz_str_trim_dup(t->text),
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"\x1b[32m0x00000007\x1b[0m \x1b[32mjmp\x1b[0m\x1b[37m \x1b[0m\x1b[33m0x1\x1b[0m\x1b[0m\x1b[0m",
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"rz_core_print_disasm text");
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rz_core_free(core);
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rz_pvector_free(vec);
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mu_end;
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}
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bool test_rz_core_print_disasm_resolve_aav_symbols() {
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RzCore *core = rz_core_new();
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mu_assert_notnull(core, "rz_core_new failed");
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RzIODesc *io_desc = rz_io_open_at(core->io, "malloc://0x200000", RZ_PERM_RWX, 0644, 0, NULL);
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mu_assert_notnull(io_desc, "io open failed");
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bool arch_configured = rz_core_arch_configure(core, "x86", 32, NULL, NULL, NULL);
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mu_assert_true(arch_configured, "rz_core_arch_configure failed");
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bool analysis_arch_set = rz_analysis_use(core->analysis, "x86");
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mu_assert_true(analysis_arch_set, "rz_analysis_use failed");
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bool analysis_bits_set = rz_analysis_set_bits(core->analysis, 32);
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mu_assert_true(analysis_bits_set, "rz_analysis_set_bits failed");
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rz_config_set_i(core->config, "scr.color", 0);
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rz_config_set_b(core->config, "asm.sub.names", true);
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rz_config_set_b(core->config, "asm.sub.rel", true);
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rz_config_set_i(core->config, "asm.sub.varmin", 0);
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ut8 code[] = { 0xa1, 0x20, 0x00, 0x10, 0x00 }; // mov eax, dword [0x100020]
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ut8 ptr[] = { 0x40, 0x00, 0x10, 0x00 }; // *(0x100020) = 0x100040
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rz_io_write_at(core->io, 0x100020, ptr, sizeof(ptr));
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rz_flag_space_set(core->flags, "symbols");
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rz_flag_set(core->flags, "aav.0x00100020", 0x100020, 4);
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rz_flag_set(core->flags, "obj.__stack_chk_guard", 0x100040, 4);
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RzPVector *vec = rz_pvector_new((RzPVectorFree)rz_analysis_disasm_text_free);
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mu_assert_notnull(vec, "rz_core_print_disasm vec not null");
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RzCoreDisasmOptions options = {
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.vec = vec,
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.cbytes = 1,
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};
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rz_core_print_disasm(core, 0, code, sizeof(code), sizeof(code), NULL, &options);
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size_t line_count = rz_pvector_len(vec);
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mu_assert_true(line_count >= 1, "rz_core_print_disasm should produce at least one line");
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RzAnalysisDisasmText *t = rz_pvector_at(vec, 0);
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mu_assert_notnull(t, "first disasm line");
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char *insn = rz_str_dup(t->text);
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mu_assert_notnull(insn, "instruction line copy");
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char *comment = strchr(insn, ';');
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if (comment) {
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*comment = '\0';
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}
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mu_assert_strcontains(insn, "obj.__stack_chk_guard", "aav.aav symbol should be resolved to preferred symbol");
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char *aav_symbol = strstr(insn, "aav.aav.");
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mu_assert_null(aav_symbol, "aav.aav symbol should not be present in instruction operand");
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free(insn);
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rz_core_free(core);
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rz_pvector_free(vec);
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mu_end;
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}
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int all_tests() {
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mu_run_test(test_rz_analysis_op_val);
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mu_run_test(test_rz_core_analysis_bytes);
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mu_run_test(test_rz_core_print_disasm);
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mu_run_test(test_rz_core_print_disasm_resolve_aav_symbols);
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return tests_passed != tests_run;
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}
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mu_main(all_tests)
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