90 lines
1.7 KiB
C
90 lines
1.7 KiB
C
/*
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handling exceptions
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http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0311d/I30195.html
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//-----//
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Flags
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Conditional instructions:
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EQ = Z
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NE = z
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CS HS = C
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CC LO = c
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MI = N // negative
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PL = n // positive
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VS = V // overflow
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VC = v // no overflow
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// unsigned
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HI = zC (!z && c)
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LS = Z || c (z || !c)
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// signed
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GE = NV || nv ((n&&v) || (!n&&!v))
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GT = NzV || nzv ((n&&!z&&v) || (!n&&!z&&!v))
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LT = Nv || nV ((n&&!v)|| (!n&&v))
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LE = Z || Nv || nV z || (n&&!v) || (!n && v)
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// INTEL X86 additions
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// - Parity flag (lsb A)
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// - counter register value != 0 (cx/ecx)
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http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0153n/CHDJEBEC.html
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Fields:
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=======
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31 n - negative (msb bit set)
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30 z - zero (== 0)
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29 c - carry
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28 v - signed overflow
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27 q - underflow
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...
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24 j - Jazzele mode
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...
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19 ge3 - ??
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18 ge2 - ??
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17 ge1 - ??
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16 ge0 - ??
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...
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9 e - Endianness (big endian if set)
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8 a - if set disables the impreceise aborts
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7 i - IRQs disabled if set
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6 f - FIQ interrupts disabled if set
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5 t - Thumb mode if set
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...
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4 m4 - ??
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3 m3
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2 m2
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1 m1
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0 m0
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int armflag_N = (Cpsr>>31)&1;
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int armflag_Z = (Cpsr>>30)&1;
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int armflag_C = (Cpsr>>29)&1;
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int armflag_V = (Cpsr>>28)&1;
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int armflag_Q = (Cpsr>>27)&1;
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int armflag_J = (Cpsr>>24)&1;
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int armflag_GE = (Cpsr>>16)&7;
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int armflag_E = (Cpsr>>9)&1;
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int armflag_A = (Cpsr>>8)&1;
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int armflag_I = (Cpsr>>7)&1;
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int armflag_F = (Cpsr>>6)&1;
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int armflag_T = (Cpsr>>5)&1;
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int armflag_M = (Cpsr>>0)&15;
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state: JT bits:
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ARM 0 (t) 0 (j)
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Thumb 1 (T) 0 (j)
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Btecode 0 (t) 1 (J)
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ThumbEE 1 (T) 1 (J)
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*/
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BX LR = {
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int tbit = reg[14] & 1;
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reg[15] = reg[14] & ~1;
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if (tbit) reg[16] |= 1<<5;
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}
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