123 lines
2.4 KiB
C
123 lines
2.4 KiB
C
// 32bit host debugging 32bit target
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return strdup (
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"=PC eip\n"
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"=SP esp\n"
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"=BP ebp\n"
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"=A0 eax\n"
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"=A1 ebx\n"
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"=A2 ecx\n"
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"=A3 edx\n"
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"=SN oeax\n"
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"gpr eax .32 24 0\n"
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"gpr ax .16 24 0\n"
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"gpr ah .8 25 0\n"
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"gpr al .8 24 0\n"
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"gpr ebx .32 0 0\n"
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"gpr bx .16 0 0\n"
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"gpr bh .8 1 0\n"
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"gpr bl .8 0 0\n"
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"gpr ecx .32 4 0\n"
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"gpr cx .16 4 0\n"
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"gpr ch .8 5 0\n"
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"gpr cl .8 4 0\n"
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"gpr edx .32 8 0\n"
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"gpr dx .16 8 0\n"
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"gpr dh .8 9 0\n"
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"gpr dl .8 8 0\n"
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"gpr esi .32 12 0\n"
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"gpr si .16 12 0\n"
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"gpr edi .32 16 0\n"
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"gpr di .16 16 0\n"
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"gpr esp .32 60 0\n"
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"gpr sp .16 60 0\n"
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"gpr ebp .32 20 0\n"
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"gpr bp .16 20 0\n"
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"gpr eip .32 48 0\n"
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"gpr ip .16 48 0\n"
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"seg@gpr xfs .32 36 0\n"
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"seg@gpr xgs .32 40 0\n"
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"seg@gpr xcs .32 52 0\n"
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"seg@gpr cs .16 52 0\n"
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"seg@gpr xss .32 52 0\n"
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"gpr eflags .32 56 0 c1p.a.zstido.n.rv\n"
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"gpr flags .16 56 0\n"
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"gpr cf .1 .448 0 carry\n"
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"gpr pf .1 .450 0 parity\n"
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"gpr af .1 .452 0 adjust\n"
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"gpr zf .1 .454 0 zero\n"
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"gpr sf .1 .455 0 sign\n"
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"gpr tf .1 .456 0 trap\n"
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"gpr if .1 .457 0 interrupt\n"
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"gpr df .1 .458 0 direction\n"
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"gpr of .1 .459 0 overflow\n"
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"gpr oeax .32 44 0\n"
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"drx dr0 .32 0 0\n"
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"drx dr1 .32 4 0\n"
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"drx dr2 .32 8 0\n"
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"drx dr3 .32 12 0\n"
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//"drx dr4 .32 16 0\n"
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//"drx dr5 .32 20 0\n"
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"drx dr6 .32 24 0\n"
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"drx dr7 .32 28 0\n"
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/*struct user_fpxregs_struct
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{
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unsigned short int cwd;
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unsigned short int swd;
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unsigned short int twd;
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unsigned short int fop;
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long int fip;
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long int fcs;
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long int foo;
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long int fos;
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long int mxcsr;
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long int reserved;
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long int st_space[32]; // 8*16 bytes for each FP-reg = 128 bytes
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long int xmm_space[32]; // 8*16 bytes for each XMM-reg = 128 bytes
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long int padding[56];
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};*/
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"fpu cwd .16 0 0\n"
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"fpu swd .16 2 0\n"
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"fpu twd .16 4 0\n"
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"fpu fop .16 6 0\n"
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"fpu fip .32 8 0\n"
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"fpu fcs .32 12 0\n"
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"fpu foo .32 16 0\n"
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"fpu fos .32 20 0\n"
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"fpu mxcsr .32 24 0\n"
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"fpu st0 .64 32 0\n"
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"fpu st1 .64 48 0\n"
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"fpu st2 .64 64 0\n"
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"fpu st3 .64 80 0\n"
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"fpu st4 .64 96 0\n"
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"fpu st5 .64 112 0\n"
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"fpu st6 .64 128 0\n"
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"fpu st7 .64 144 0\n"
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"fpu xmm0h .64 160 0\n"
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"fpu xmm0l .64 168 0\n"
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"fpu xmm1h .64 176 0\n"
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"fpu xmm1l .64 184 0\n"
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"fpu xmm2h .64 192 0\n"
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"fpu xmm2l .64 200 0\n"
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"fpu xmm3h .64 208 0\n"
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"fpu xmm3l .64 216 0\n"
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"fpu xmm4h .64 224 0\n"
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"fpu xmm4l .64 232 0\n"
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"fpu xmm5h .64 240 0\n"
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"fpu xmm5l .64 248 0\n"
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"fpu xmm6h .64 256 0\n"
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"fpu xmm6l .64 264 0\n"
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"fpu xmm7h .64 272 0\n"
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"fpu xmm7l .64 280 0\n"
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"fpu x86 .64 288 0\n"
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);
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