622e828e1d
* Add basic support for N64 RSP processor. This includes: * a table driven instruction decoder (rsp_idec) * a disassembler * a very primitive anal plugin
179 lines
3.3 KiB
C
179 lines
3.3 KiB
C
/* radare - LGPL - Copyright 2016 - bobby.smiles32@gmail.com */
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#ifndef R_ASM_ARCH_RSP_RSP_IDEC_H
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#define R_ASM_ARCH_RSP_RSP_IDEC_H
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#include <r_types.h>
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extern const char* rsp_gp_reg_soft_names[];
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extern const char* rsp_c0_reg_soft_names[];
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extern const char* rsp_gp_reg_names[];
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extern const char* rsp_c0_reg_names[];
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extern const char* rsp_c2_creg_names[];
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extern const char* rsp_c2_accu_names[];
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extern const char* rsp_c2_vreg_names[];
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extern const char* rsp_c2_vreg_element_names[];
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enum {
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RSP_DMEM_OFFSET = 0x0000,
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RSP_IMEM_OFFSET = 0x1000
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};
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/* restrict address inside rsp MEM */
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static inline ut64 rsp_mem_addr(ut64 addr, ut64 base) { addr &= 0xfff; addr |= base; return addr; }
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typedef enum {
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RSP_OP_INVALID,
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RSP_OP_NOP,
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RSP_OP_SLL,
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RSP_OP_SRL,
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RSP_OP_SRA,
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RSP_OP_SLLV,
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RSP_OP_SRLV,
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RSP_OP_SRAV,
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RSP_OP_JR,
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RSP_OP_BREAK,
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RSP_OP_ADD,
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RSP_OP_ADDU,
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RSP_OP_SUB,
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RSP_OP_SUBU,
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RSP_OP_AND,
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RSP_OP_OR,
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RSP_OP_XOR,
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RSP_OP_NOR,
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RSP_OP_SLT,
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RSP_OP_SLTU,
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RSP_OP_BLTZ,
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RSP_OP_BGEZ,
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RSP_OP_BLTZAL,
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RSP_OP_BGEZAL,
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RSP_OP_MFC0,
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RSP_OP_MTC0,
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RSP_OP_MFC2,
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RSP_OP_MTC2,
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RSP_OP_CFC2,
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RSP_OP_CTC2,
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RSP_OP_VMULF,
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RSP_OP_VMULU,
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RSP_OP_VMUDL,
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RSP_OP_VMUDM,
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RSP_OP_VMUDN,
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RSP_OP_VMUDH,
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RSP_OP_VMACF,
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RSP_OP_VMACU,
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RSP_OP_VMADL,
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RSP_OP_VMADM,
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RSP_OP_VMADN,
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RSP_OP_VMADH,
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RSP_OP_VADD,
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RSP_OP_VSUB,
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RSP_OP_VABS,
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RSP_OP_VADDC,
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RSP_OP_VSUBC,
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RSP_OP_VSAR,
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RSP_OP_VLT,
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RSP_OP_VEQ,
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RSP_OP_VNE,
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RSP_OP_VGE,
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RSP_OP_VCL,
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RSP_OP_VCH,
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RSP_OP_VCR,
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RSP_OP_VMRG,
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RSP_OP_VAND,
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RSP_OP_VNAND,
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RSP_OP_VOR,
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RSP_OP_VNOR,
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RSP_OP_VXOR,
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RSP_OP_VNXOR,
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RSP_OP_VRCP,
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RSP_OP_VRCPL,
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RSP_OP_VRCPH,
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RSP_OP_VMOV,
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RSP_OP_VRSQ,
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RSP_OP_VRSQL,
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RSP_OP_VRSQH,
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RSP_OP_VNOP,
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RSP_OP_LBV,
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RSP_OP_LSV,
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RSP_OP_LLV,
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RSP_OP_LDV,
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RSP_OP_LQV,
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RSP_OP_LRV,
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RSP_OP_LPV,
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RSP_OP_LUV,
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RSP_OP_LHV,
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RSP_OP_LFV,
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RSP_OP_LTV,
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RSP_OP_SBV,
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RSP_OP_SSV,
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RSP_OP_SLV,
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RSP_OP_SDV,
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RSP_OP_SQV,
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RSP_OP_SRV,
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RSP_OP_SPV,
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RSP_OP_SUV,
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RSP_OP_SHV,
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RSP_OP_SFV,
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RSP_OP_SWV,
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RSP_OP_STV,
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RSP_OP_J,
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RSP_OP_JAL,
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RSP_OP_BEQ,
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RSP_OP_BNE,
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RSP_OP_BLEZ,
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RSP_OP_BGTZ,
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RSP_OP_ADDI,
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RSP_OP_ADDIU,
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RSP_OP_SLTI,
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RSP_OP_SLTIU,
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RSP_OP_ANDI,
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RSP_OP_ORI,
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RSP_OP_XORI,
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RSP_OP_LUI,
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RSP_OP_LB,
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RSP_OP_LH,
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RSP_OP_LW,
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RSP_OP_LBU,
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RSP_OP_LHU,
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RSP_OP_SB,
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RSP_OP_SH,
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RSP_OP_SW
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} rsp_opcode;
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typedef enum {
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RSP_OPND_GP_REG, /* u=reg_num */
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RSP_OPND_TARGET, /* u=imem_address */
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RSP_OPND_OFFSET, /* u=imem_address, s=offset */
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RSP_OPND_ZIMM, /* u=zero-extended imm */
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RSP_OPND_SIMM, /* s=sign extended imm */
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RSP_OPND_SHIFT_AMOUNT, /* u=shift amount */
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RSP_OPND_BASE_OFFSET, /* u=reg_numm, s=offset */
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RSP_OPND_C0_REG, /* u=reg_num */
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RSP_OPND_C2_CREG, /* u=reg_num */
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RSP_OPND_C2_ACCU, /* u=reg_num */
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RSP_OPND_C2_VREG, /* u=reg_num */
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RSP_OPND_C2_VREG_BYTE, /* u=reg_num, s=byte element (0-15) */
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RSP_OPND_C2_VREG_SCALAR, /* u=reg_num, s=scalar element (0-7) */
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RSP_OPND_C2_VREG_ELEMENT /* u=reg_num, s=element (0-15) */
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} rsp_operand_type;
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typedef struct {
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rsp_operand_type type;
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ut64 u;
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st64 s;
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} rsp_operand;
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enum { RSP_MAX_OPNDS = 3 };
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typedef struct {
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const char* mnemonic;
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rsp_opcode opcode;
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int noperands;
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rsp_operand operands[RSP_MAX_OPNDS];
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} rsp_instruction;
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rsp_instruction rsp_instruction_decode(ut64 pc, ut32 iw);
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#endif
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