622e828e1d
* Add basic support for N64 RSP processor. This includes: * a table driven instruction decoder (rsp_idec) * a disassembler * a very primitive anal plugin
121 lines
3.2 KiB
C
121 lines
3.2 KiB
C
/* radare - LGPL - Copyright 2016 - bobby.smiles32@gmail.com */
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// TODO: add assembler
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#include <r_types.h>
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#include <r_util.h>
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#include <r_asm.h>
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#include <r_lib.h>
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#include <stdarg.h>
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#include <stdio.h>
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#include "rsp_idec.h"
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static void snappendf(char** dst, size_t* size, const char* format, ...) {
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size_t n;
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va_list va;
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va_start (va, format);
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n = vsnprintf (*dst, *size, format, va);
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*dst += n;
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*size -= n;
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va_end (va);
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}
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static int disassemble(RAsm *a, RAsmOp *op, const ut8 *buf, int len) {
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ut32 iw;
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rsp_instruction r_instr;
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int i;
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char* buffer;
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size_t size;
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/* all instructions are 32bit words */
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if (len < 4) {
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op->size = 0;
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return 0;
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}
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op->size = 4;
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iw = r_read_ble32 (buf, a->big_endian);
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r_instr = rsp_instruction_decode (a->pc, iw);
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buffer = op->buf_asm;
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size = sizeof (op->buf_asm);
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snappendf (&buffer, &size, r_instr.mnemonic);
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for (i = 0; i < r_instr.noperands; ++i) {
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snappendf (&buffer, &size, "%s", (i == 0) ? " " : ", ");
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switch (r_instr.operands[i].type) {
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case RSP_OPND_GP_REG:
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snappendf (&buffer, &size, "%s", rsp_gp_reg_soft_names[r_instr.operands[i].u]);
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break;
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case RSP_OPND_OFFSET:
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case RSP_OPND_TARGET:
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snappendf (&buffer, &size, "0x%08x", r_instr.operands[i].u);
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break;
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case RSP_OPND_ZIMM:
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snappendf (&buffer, &size, "0x%04x", r_instr.operands[i].u >> ((r_instr.operands[i].u & ~0xffff) ? 16 : 0));
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break;
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case RSP_OPND_SIMM:
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snappendf (&buffer, &size, "%s0x%04x",
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(r_instr.operands[i].s<0)?"-":"",
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(r_instr.operands[i].s<0)?-r_instr.operands[i].s:r_instr.operands[i].s);
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break;
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case RSP_OPND_SHIFT_AMOUNT:
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snappendf (&buffer, &size, "%u", r_instr.operands[i].u);
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break;
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case RSP_OPND_BASE_OFFSET:
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snappendf (&buffer, &size, "%s0x%04x(%s)",
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(r_instr.operands[i].s<0)?"-":"",
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(r_instr.operands[i].s<0)?-r_instr.operands[i].s:r_instr.operands[i].s,
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rsp_gp_reg_soft_names[r_instr.operands[i].u]);
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break;
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case RSP_OPND_C0_REG:
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snappendf (&buffer, &size, "%s", rsp_c0_reg_soft_names[r_instr.operands[i].u]);
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break;
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case RSP_OPND_C2_CREG:
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snappendf (&buffer, &size, "%s", rsp_c2_creg_names[r_instr.operands[i].u]);
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break;
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case RSP_OPND_C2_ACCU:
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snappendf (&buffer, &size, "%s", rsp_c2_accu_names[r_instr.operands[i].u]);
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break;
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case RSP_OPND_C2_VREG:
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snappendf (&buffer, &size, "%s", rsp_c2_vreg_names[r_instr.operands[i].u]);
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break;
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case RSP_OPND_C2_VREG_BYTE:
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case RSP_OPND_C2_VREG_SCALAR:
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snappendf (&buffer, &size, "%s[%u]", rsp_c2_vreg_names[r_instr.operands[i].u], r_instr.operands[i].s);
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break;
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case RSP_OPND_C2_VREG_ELEMENT:
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snappendf (&buffer, &size, "%s%s", rsp_c2_vreg_names[r_instr.operands[i].u], rsp_c2_vreg_element_names[r_instr.operands[i].s]);
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break;
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default: /* should not happend */
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snappendf (&buffer, &size, "???");
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break;
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}
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}
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return op->size;
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}
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RAsmPlugin r_asm_plugin_rsp = {
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.name = "rsp",
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.desc = "Reality Signal Processor",
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.arch = "rsp",
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.bits = 32,
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.endian = R_SYS_ENDIAN_BI, /* For conveniance, we don't force BIG endian but allow both to be used */
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.license = "LGPL3",
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.disassemble = &disassemble
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};
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#ifndef CORELIB
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struct r_lib_struct_t radare_plugin = {
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.type = R_LIB_TYPE_ASM,
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.data = &r_asm_plugin_rsp,
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.version = R2_VERSION
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};
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#endif
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