rizin/test/db/analysis/tms320.c64x_32
wargio d47ceedbd3 Merge rz_asm and rz_analysis into one library but keep deprecated apis.
The tms320c64x has been merged into tms320.
2024-03-07 18:38:49 +08:00

356 lines
7.8 KiB
Text

NAME=320c64 OPEX
FILE=malloc://512280
CMDS=<<EOF
e asm.arch=tms320
e asm.cpu=c64x
wx 0041bd10
aoj~{}
EOF
EXPECT=<<EOF
[
{
"opcode": "b 0x20de8",
"disasm": "b 0x20de8",
"pseudo": "goto 0x20de8",
"mnemonic": "b",
"mask": "ff000000",
"jump": 134632,
"sign": false,
"prefix": 0,
"id": 17,
"opex": {
"operands": [
{
"type": "imm",
"value": 134632
}
]
},
"addr": 0,
"bytes": "0041bd10",
"size": 4,
"type": "jmp",
"esilcost": 0,
"scale": 0,
"refptr": 0,
"cycles": 0,
"failcycles": 0,
"delay": 0,
"stackptr": 0,
"family": "cpu"
}
]
EOF
RUN
NAME=320c64 pseudo
FILE=bins/elf/ld-2.27.so
CMDS=<<EOF
e asm.arch=tms320
e asm.cpu=c64x
e asm.pseudo=true
pi 0x100~=
EOF
EXPECT=<<EOF
a17 = (half) 0x13cf
a28 = 0 ext a0 .. 0
b23:b22 = (word) *a1++[12]
a4 = 2 ext a0 .. 0x1a
a26 = 0x4988
a4 = 0x12 .bitset a20 .. 0x12
a13:a12 = (word) *-a18[a12]
a17 = a31 avg a0
b22 = (word) *+b14[0x3da6]
a4 = (half) *+b15[0x49]
a25 = 8 ext a21 .. 0x10
a26 = a8 ~ a21
a16 = a23 * a25
b17 = (half) *+b15[0xd15]
a16 = (half) *+b14[0x0]
*+b15[0x6c41] = (word) b19
b8 = (byte) *+b14[0x660f]
b12 = (byte) *+b14[0x2e0f]
b12 = (byte) *+b14[0x2e0f]
a0 = 0x1a .bitset a20 .. 0x1a
a22 = 9 .bitclear a17 .. 9
a10 = 0xe ext a12 .. 0
a7 = 0 ext a27 .. 0x10
a22 = 0x18 ext a29 .. 8
*+b14[0x488b] = (byte) b0
a14 = 1 ext a17 .. 4
a17 = (byte) *a3--[10]
b16 = (half) -0x2c00
b4 = (half) *+b15[0x488d]
a6 = (half) 1
a30 = 0 ext a0 .. 0
a23:a22 = 1 + a20:a19
a20 = (half) *-a23[a18]
b8 += 0x2463
*-a1[14] = (word) a17
a16 = 0x1a ext a0 .. 0x11
a23 = 0x1c ext a16 .. 0x10
*+b14[0x5b1] = (word) b26
a4 = 2 ext a0 .. 0x13
b19 = 0x1a .bitset b30 .. 0x1a
b9 = (half) *+b15[0xb05]
a10 = 0x10 ext a8 .. 0
a26 = (byte) *-a5[15]
b0 = 2 .bitset b0 .. 2
a30 = (word) *+b15[0x4883]
*+b15[0x47c1] = (word) b17
*+b15[0x7fff] = (word) b31
a1 = a16 * a15
*-a3[a7] = (word) b1
a10 = 8 ext a0 .. 0
a18 = max(a24, a16)
b20 = (half) *+b14[0x5bc3]
b30 = (word) *-a16[0]
a0 = 0x10 ext a15 .. 0
a2 = 8 ext a29 .. 0x18
a23:a22 = (word) *-a1[12]
b4 = 2 .bitset b0 .. 2
*+b14[0xd05] = (half) b17
a14 = 8 ext a0 .. 0
b11 = (half) *+b14[0x4948]
a9 = (half) *+b15[0x4848]
a17 = a24 * a29
a1:a0 = a0 * a0
a26 = a0 * a1
b30 = (word) *-a7[24]
a17 = 0x18 ext a2 .. 5
a10 = 0x10 ext a8 .. 0
a19 = (half) *+b15[0x5048]
a15 = a24 * a29
a17 = 0xf ext a2 .. 0x11
*a13--(a9) = (half) b27:b26
b2 = 5 * b0
a0 = 0 ext a0 .. 0
a22 = (half) *-a0[a2]
a30 = 6 ext a17 .. 2
a4 = (half) 0x6381
a24 = a0 * a1
b13 = (byte) *+b14[0x1066]
*a16++[10] = (half) a0
b19 += 0x13fc
a17 = 0xe ext a2 .. 0x15
a26 = 0xc * a3
b0 = b2 * b0
a24 = (byte) *+b14[0x508b]
a28 = 0x10 ext a8 .. 0
a18 = 1 ext a31 .. 4
a17 = (byte) *a2--[9]
a26 = a1 * a17
a28 = 1 ext a17 .. 4
a17 = (byte) *a3--[10]
a30 = (half) *a3++[24]
a17 = (byte) *a3--[11]
*+b14[0x488d] = (word) a16
b8 = (half) *-a8[a2]
a18 = a1 * a17
*+b15[0x63fc] = (word) b16
*+a19[a4] = (half) a31:a30
*-a1[14] = (word) a27
a3 = (byte) *+b14[0x4039]
b26 = (half) *+b14[0x2200]
b11 = b2 * b16
*+b14[0x505b] = (half) a8
b2 = (half) *+b14[0x5ec3]
a8 = 0 ext a0 .. 0
a14 = 0x10 ext a0 .. 0
a19 = 0xa .bitset a26 .. 0xa
*+b15[0x31c0] = (byte) b4
a0 = (half) 1
a14 = a24 * a0
a17 += 0x788
*+b14[0x405b] = (half) a3
b3:b2 = (word) *+a23[22]
b0 = (half) *+b14[0x662e]
b0 = 0x1a .bitset b20 .. 0x1a
a14 = 2 .bitset a4 .. 2
b22 = b4 - b18
a17 = 0x1b ext a2 .. 0x1f
a3 = a18 * a20
a31 = (half) *+a5[14]
a3 = 9 .bitclear a18 .. 9
a20 = 0 ext a0 .. 0
b18 = max(b24, b16)
*a3++[a24] = (half) a7:a6
*-a0[2] = (word) b0
*-a21[18] = (word) a2
a2 = (half) *+b15[0x544c]
a26 = a15 * a8
a0 = 0xa ext a21 .. 0x13
a19 = a2 * a31
a0 = 0 ext a0 .. 0
*+b15[0xf48] = (byte) b22
a27 = (half) *+b15[0x4ccc]
a25 = (half) *+b15[0x4ccc]
a19 = 0xf ext a2 .. 6
a17 = 0xe ext a2 .. 8
a7 = 0x10 ext a27 .. 1
a15 = a25 - a26
a20 = (half) *+b15[0x348]
a16 = 0xe ext a0 .. 0
a19 = (half) *-a16[a10]
a2 = (half) *a3++[29]
a26 = 2 .bitset a0 .. 2
a12 = 0xe ext a29 .. 0x18
a12 = 5 .bitclear a5 .. 5
a0 = (half) *+b14[0x0]
a16 = (half) *+b14[0x29f0]
*+b14[0x7f48] = (byte) a19
a0 = 0 ext a0 .. 0
b30 = b30 * b17
a16 = 2 .bitset a2 .. 2
a0 = 0x10 .bitset a28 .. 0x10
b3 = b15 * b16
a7:a6 = a5 * a18
EOF
RUN
NAME=arp TMS320
FILE==
CMDS=<<EOF
e asm.arch=tms320
e asm.cpu=c64x
arp
EOF
EXPECT=<<EOF
=PC pc
=A0 a4
=A1 b4
=A2 a6
=A3 a6
=A4 a8
=A5 b8
=A6 a10
=A7 b10
=A8 a12
=A9 b12
=R0 a4
gpr a0 .32 0 0
gpr a1 .32 4 0
gpr a2 .32 8 0
gpr a3 .32 12 0
gpr a4 .32 16 0
gpr a5 .32 20 0
gpr a6 .32 24 0
gpr a7 .32 28 0
gpr a8 .32 32 0
gpr a9 .32 36 0
gpr a10 .32 40 0
gpr a11 .32 44 0
gpr a12 .32 48 0
gpr a13 .32 52 0
gpr a14 .32 56 0
gpr a15 .32 60 0
gpr a16 .32 64 0
gpr a17 .32 68 0
gpr a18 .32 72 0
gpr a19 .32 76 0
gpr a20 .32 80 0
gpr a21 .32 84 0
gpr a22 .32 88 0
gpr a23 .32 92 0
gpr a24 .32 96 0
gpr a25 .32 100 0
gpr a26 .32 104 0
gpr a27 .32 108 0
gpr a28 .32 112 0
gpr a29 .32 116 0
gpr a30 .32 120 0
gpr a31 .32 124 0
gpr b0 .32 128 0
gpr b1 .32 132 0
gpr b2 .32 136 0
gpr b3 .32 140 0
gpr b4 .32 144 0
gpr b5 .32 148 0
gpr b6 .32 152 0
gpr b7 .32 156 0
gpr b8 .32 160 0
gpr b9 .32 164 0
gpr b10 .32 168 0
gpr b11 .32 172 0
gpr b12 .32 176 0
gpr b13 .32 180 0
gpr b14 .32 184 0
gpr b15 .32 188 0
gpr b16 .32 192 0
gpr b17 .32 196 0
gpr b18 .32 200 0
gpr b19 .32 204 0
gpr b20 .32 208 0
gpr b21 .32 212 0
gpr b22 .32 216 0
gpr b23 .32 220 0
gpr b24 .32 224 0
gpr b25 .32 228 0
gpr b26 .32 232 0
gpr b27 .32 236 0
gpr b28 .32 240 0
gpr b29 .32 244 0
gpr b30 .32 248 0
gpr b31 .32 252 0
ctr amr .32 256 0 # Addressing mode register
ctr csr .32 260 0 # Control status register
ctr gfpgfr .32 264 0 # Galois field multiply control register
ctr icr .32 268 0 # Interrupt clear register
ctr ier .32 272 0 # Interrupt enable register
ctr ifr .32 276 0 # Interrupt flag register
ctr irp .32 280 0 # Interrupt return pointer register
ctr isr .32 284 0 # Interrupt set register
ctr istp .32 288 0 # Interrupt service table pointer register
ctr nrp .32 292 0 # Nonmaskable interrupt return pointer register
ctr pce1 .32 296 0 # Program counter, E1 phase
ctr dier .32 300 0 # (C64x+ only) Debug interrupt enable register
ctr dnum .32 304 0 # (C64x+ only) DSP core number register
ctr ecr .32 308 0 # (C64x+ only) Exception clear register
ctr efr .32 312 0 # (C64x+ only) Exception flag register
ctr gplya .32 316 0 # (C64x+ only) GMPY A-side polynomial register
ctr gplyb .32 320 0 # (C64x+ only) GMPY B-side polynomial register
ctr ierr .32 324 0 # (C64x+ only) Internal exception report register
ctr ilc .32 328 0 # (C64x+ only) Inner loop count register
ctr itsr .32 332 0 # (C64x+ only) Interrupt task state register
ctr ntsr .32 336 0 # (C64x+ only) NMI/Exception task state register
ctr rep .32 340 0 # (C64x+ only) Restricted entry point address register
ctr rilc .32 344 0 # (C64x+ only) Reload inner loop count register
ctr ssr .32 348 0 # (C64x+ only) Saturation status register
ctr tsch .32 352 0 # (C64x+ only) Time-stamp counter (high 32) register
ctr tscl .32 356 0 # (C64x+ only) Time-stamp counter (low 32) register
ctr tsr .32 360 0 # (C64x+ only) Task state register
gpr a0:a1 .64 364 0
gpr a2:a3 .64 368 0
gpr a4:a5 .64 372 0
gpr a6:a7 .64 376 0
gpr a8:a9 .64 380 0
gpr a10:a11 .64 384 0
gpr a12:a13 .64 388 0
gpr a14:a15 .64 392 0
gpr a16:a17 .64 396 0
gpr a18:a19 .64 400 0
gpr a20:a21 .64 404 0
gpr a22:a23 .64 408 0
gpr a24:a25 .64 412 0
gpr a26:a27 .64 416 0
gpr a28:a29 .64 420 0
gpr a30:a31 .64 424 0
gpr b0:b1 .64 428 0
gpr b2:b3 .64 432 0
gpr b4:b5 .64 436 0
gpr b6:b7 .64 440 0
gpr b8:b9 .64 444 0
gpr b10:b11 .64 448 0
gpr b12:b13 .64 452 0
gpr b14:b15 .64 456 0
gpr b16:b17 .64 460 0
gpr b18:b19 .64 464 0
gpr b20:b21 .64 468 0
gpr b22:b23 .64 472 0
gpr b24:b25 .64 476 0
gpr b26:b27 .64 480 0
gpr b28:b29 .64 484 0
gpr b30:b31 .64 488 0
EOF
RUN