399 lines
13 KiB
C
399 lines
13 KiB
C
// SPDX-FileCopyrightText: 1994, 1995 Myricom, Inc.
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// SPDX-License-Identifier: GPL-2.0-only
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/*************************************************************************
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* *
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* Definitions for opcode table for the Lanai. *
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* *
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* Copyright (c) 1994, 1995 by Myricom, Inc. *
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* All rights reserved. *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of version 2 of the GNU General Public License *
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* as published by the Free Software Foundation. Myricom requests that *
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* all modifications of this software be returned to Myricom, Inc. for *
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* redistribution. The name of Myricom, Inc. may not be used to endorse *
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* or promote products derived from this software without specific prior *
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* written permission. *
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* *
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* Myricom, Inc. makes no representations about the suitability of this *
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* software for any purpose. *
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* *
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* THIS FILE IS PROVIDED "AS-IS" WITHOUT WARRANTY OF ANY KIND, WHETHER *
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* EXPRESSED OR IMPLIED, INCLUDING THE WARRANTY OF MERCHANTABILITY OR *
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* FITNESS FOR A PARTICULAR PURPOSE. MYRICOM, INC. SHALL HAVE NO *
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* LIABILITY WITH RESPECT TO THE INFRINGEMENT OF COPYRIGHTS, TRADE *
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* SECRETS OR ANY PATENTS BY THIS FILE OR ANY PART THEREOF. *
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* *
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* In no event will Myricom, Inc. be liable for any lost revenue *
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* or profits or other special, indirect and consequential damages, even *
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* if Myricom has been advised of the possibility of such damages. *
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* *
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* Other copyrights might apply to parts of this software and are so *
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* noted when applicable. *
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* *
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* Myricom, Inc. Email: info@myri.com *
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* 325 N. Santa Anita Ave. World Wide Web: http://www.myri.com/ *
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* Arcadia, CA 91024 *
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*************************************************************************/
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/* initial version released 5/95 */
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/* This file is based upon sparc.h from the Gnu binutils-2.5.2
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release, which had the following copyright notice: */
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/* Definitions for opcode table for the sparc.
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Copyright 1989, 1991, 1992 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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the GNU Binutils.
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GAS/GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS/GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS or GDB; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139,
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USA. */
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/* The Lanai opcode table (and other related data) is defined in
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the opcodes library in lanai-opc.c. If you change anything here, make
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sure you fix up that file, and vice versa. */
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/* FIXME-someday: perhaps the ,a's and such should be embedded in the
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instruction's name rather than the args. This would make gas faster, pinsn
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slower, but would mess up some macros a bit. xoxorich. */
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#define lanai_architecture bfd_lanai_architecture
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#define architecture_pname bfd_lanai_architecture_pname
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#define lanai_opcode bfd_lanai_opcode
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#define lanai_opcodes bfd_lanai_opcodes
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/*
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* Structure of an opcode table entry.
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* This enumerator must parallel the architecture_pname array
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* in bfd/opc-lanai.c.
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*/
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enum lanai_architecture {
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v0 = 0,
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v1
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};
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extern const char *architecture_pname[];
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struct lanai_opcode {
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const char *name;
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unsigned long match; /* Bits that must be set. */
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unsigned long lose; /* Bits that must be clear. */
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const char *args;
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unsigned int flags;
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enum lanai_architecture architecture;
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};
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#define F_ALIAS 1 /* Alias for a "real" instruction */
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#define F_JSR 2 /* Subroutine call */
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#define F_RI 0x10
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#define F_RR 0x20
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#define F_RRR 0x40
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#define F_RM 0x80
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#define F_RRM 0x100
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#define F_BR 0x200
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#define F_SLS 0x400
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#define F_SLI 0x800
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#define F_SPLS 0x1000
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#define F_PUNT 0x2000
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#define F_SBR 0x4000
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#define F_SCC 0x8000
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#define F_BYTE 0x20000
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#define F_HALF 0x10000
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#define F_FULL 0x00000
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#define F_DATA_SIZE(X) (4 >> ((X)&0x30000))
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#define F_CONDITIONAL 0x40000
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#define F_REL 0x80000
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#define F_LEADZ 0x100000
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#define F_POPC 0x200000
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#define F_CONDBR (F_BR | F_CONDITIONAL) /* Conditional branch */
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#define F_UNBR (F_BR) /* Unconditional branch */
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#define F_RELCONDBR (F_REL | F_BR | F_CONDITIONAL) /* Conditional branch */
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#define F_RELUNBR (F_REL | F_BR) /* Unconditional branch */
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/* FIXME: Add F_ANACHRONISTIC flag for v9. */
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/* FIXME: Add F_OBSOLETE flag for v9, for instructions that no longer exist? */
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/*
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All lanai opcodes are 32 bits.
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The match component is a mask saying which bits must match a particular
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opcode in order for an instruction to be an instance of that opcode.
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The args component is a string containing one character for each operand of the
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instruction.
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Kinds of operands:
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# Number used by optimizer. It is ignored.
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1 Rs1 register.
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2 Rs2 register.
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3 Rs3 register.
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d Rd register.
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4 Op1 (for RRR)
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5 Op2 (for RRR)
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6 Op2 (for RRM)
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J 0x????0000
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j 0x0000????
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L 0x????ffff
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l 0xffff????
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k -j
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o 16 bit signed offset
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s 6 bit signed shift constant
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i 10 bit signed immediate.
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I 5/16 split 21-bit unsigned immediate.
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Y 5/16 split 21-bit unsigned immediate with 2 LSB's == 0.
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B 2+23-bit absolute.
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b 2+23-bit PC relative immediate.
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P %pc or %r2 as Rd
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p %pc or %r2 as Rs1
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X Q %apc or %r29
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X q %aps or %r28
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X S %isr or %r31
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X M %imr or %r30
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! %r1
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0 %r0
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Literals:([])*+- ,
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*/
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/* whether to use certain insns */
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#define L3_USE_SI
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#define L3_USE_SPLS
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#define L3_USE_SLS
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#define L3_USE_SLI
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#define L3_USE_SBR
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/* encodings of various conditions */
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#define L3_T 0
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#define L3_F 1
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#define L3_HI 2
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#define L3_LS 3
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#define L3_CC 4
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#define L3_CS 5
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#define L3_NE 6
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#define L3_EQ 7
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#define L3_VC 8
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#define L3_VS 9
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#define L3_PL 10
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#define L3_MI 11
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#define L3_GE 12
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#define L3_LT 13
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#define L3_GT 14
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#define L3_LE 15
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#define L3_UGE L3_CC
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#define L3_ULT L3_CS
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#define L3_UGT L3_GT
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#define L3_ULE L3_LE
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/* opcodes */
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/* NOTE: The following masks specify all the bits that can be
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determined solely by knowing which line in lanai-opc.c (in the opcodes
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directory in the gnu binutils release) matched the line of assembly
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code. The OPCODE_MASK specifies which bits of the instruction are constant
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for all instructions in the family.
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*/
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#define L3_RI (0x00000000)
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#define L3_RI_OPCODE_MASK (0x80000000)
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#define L3_RI_MASK (0xf0030000)
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#define L3_RR (0xc0000000)
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#define L3_RR_OPCODE_MASK (0xf0000003)
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#define L3_RR_MASK (0xf00207fb)
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#define L3_LEADZ (0xc0000002)
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#define L3_LEADZ_OPCODE_MASK L3_RR_OPCODE_MASK
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#define L3_LEADZ_MASK (0xf00207fb)
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#define L3_POPC (0xc0000003)
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#define L3_POPC_OPCODE_MASK L3_RR_OPCODE_MASK
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#define L3_POPC_MASK (0xf00207fb)
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#define L3_RRR (0xd0000000)
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#define L3_RRR_OPCODE_MASK (0xf0000000)
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#define L3_RRR_MASK (0xf0000000)
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#define L3_RM (0x80000000)
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#define L3_RM_OPCODE_MASK (0xe0000000)
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#define L3_RM_MASK (0xf0030000)
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#define L3_RRM (0xa0000000)
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#define L3_RRM_OPCODE_MASK (0xe0000000)
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#define L3_RRM_MASK (0xe0030007)
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#define L3_BR (0xe0000000)
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#define L3_BR_OPCODE_MASK (0xf0000002)
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#define L3_BR_MASK (0xfe000003)
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#define L3_BRR (0xe1000002)
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#define L3_BRR_OPCODE_MASK (0xf1000002)
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#define L3_BRR_MASK (0xff000003)
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#define L3_SCC (0xe0000002)
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#define L3_SCC_OPCODE_MASK (0xf1000002)
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#define L3_SCC_MASK (0xff000003)
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#define L3_SLS (0xf0000000)
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#define L3_SLS_OPCODE_MASK (0xf0020000)
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#define L3_SLS_MASK (0xf0030000)
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#define L3_SLI (0xf0020000)
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#define L3_SLI_OPCODE_MASK (0xf0030000)
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#define L3_SLI_MASK (0xf0030000)
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#define L3_SPLS (0xf0030000)
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#define L3_SPLS_OPCODE_MASK (0xf0038000)
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#define L3_SPLS_MASK (0xf003fc00)
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#ifdef BAD
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/* BAD: needs fixing */
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#define L3_SI (0xf0038000)
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#define L3_SI_OPCODE_MASK ___bogus___
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#define L3_SI_MASK (0xf003cf47)
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#endif
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#define L3_PUNT (0xf003ff47)
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#define L3_PUNT_OPCODE_MASK (0xf003ff47)
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#define L3_PUNT_MASK (0xf003ff47)
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#define L3_SBR (0xf003c000)
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#define L3_SBR_OPCODE_MASK (0xf003f806)
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#define L3_SBR_MASK (0xfe03f807)
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/* operations */
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#define L3_ADD (0x00)
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#define L3_ADDC (0x01)
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#define L3_SUB (0x02)
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#define L3_SUBB (0x03)
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#define L3_AND (0x04)
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#define L3_OR (0x05)
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#define L3_XOR (0x06)
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#define L3_SH (0x07)
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#define L3_OP_MASK (0x07)
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#define L3_FLAGS (0x08)
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#define L3_ARITH (0x10)
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/* Data sizes */
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#define L3_HALFWORD 0
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#define L3_BYTE 4 /* was 1 */
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#define L3_FULLWORD 2
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/* RRM modes for BYTE and HALFWORD load */
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#define L3_SIGNED 0
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#define L3_UNSIGNED 1 /* was 4 */
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#define L3_SIGNED_HALFWORD (L3_SIGNED | L3_HALFWORD)
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#define L3_SIGNED_BYTE (L3_SIGNED | L3_BYTE)
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#define L3_SIGNED_FULLWORD (L3_SIGNED | L3_FULLWORD)
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#define L3_UNSIGNED_HALFWORD (L3_UNSIGNED | L3_HALFWORD)
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#define L3_UNSIGNED_BYTE (L3_UNSIGNED | L3_BYTE)
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#define L3_UNSIGNED_FULLWORD (L3_UNSIGNED | L3_FULLWORD)
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/* flags */
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#define L3_RI_F (0x00020000)
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#define L3_RI_H (0x00010000)
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#define L3_RR_F (0x00020000)
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#define L3_LEADZ_F L3_RR_F
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#define L3_POPC_F L3_RR_F
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#define L3_RRR_F (0x00020000)
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#define L3_RRR_H (0x00010000)
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#define L3_RM_P (0x00020000)
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#define L3_RM_Q (0x00010000)
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#define L3_RM_S (0x10000000)
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#define L3_RRM_P (0x00020000)
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#define L3_RRM_Q (0x00010000)
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#define L3_RRM_S (0x10000000)
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#define L3_RRM_Y (0x00000004)
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#define L3_RRM_L (0x00000002)
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#define L3_RRM_E (0x00000001)
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#define L3_BR_R (0x00000002)
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#define L3_SLS_S (0x00010000)
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#define L3_SPLS_Y (0x00004000)
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#define L3_SPLS_S (0x00002000)
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#define L3_SPLS_E (0x00001000)
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#define L3_SPLS_P (0x00000800)
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#define L3_SPLS_Q (0x00000400)
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#define L3_SI_F (0x00002000)
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#define L3_SBR_H (0x00000004)
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#define L3_SBR_R (0x00000002)
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#define L3_SBR_N (0x00000001)
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/* masks */
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#define L3_CONST_MASK (0x0000ffff)
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#define L3_BR_CONST_MASK (0x01fffffc)
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#define L3_SPLS_CONST_MASK (0x000003ff)
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/* field insertion */
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#define L3_RD(x) (((x)&0x1f) << 23)
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#define L3_RS1(x) (((x)&0x1f) << 18)
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#define L3_RS2(x) (((x)&0x1f) << 11)
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#define L3_RS3(x) (((x)&0x1f) << 3)
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#define L3_RI_OP(x) (((x)&L3_OP_MASK) << 28)
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#define L3_RR_OP(x) (((x)&L3_OP_MASK) << 8)
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#define L3_RRR_OP1(x) (((x)&L3_OP_MASK) << 0)
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#define L3_RRR_OP2(x) (((x)&L3_OP_MASK) << 8)
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#define L3_RRM_OP(x) (((x)&L3_OP_MASK) << 8)
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#define L3_RRM_MODE(x) (((x)&0x7) << 0)
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#define L3_BR_COND(x) ((((x)&0xe) << 24) | ((x)&1))
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#define L3_SBR_COND(x) ((((x)&0xe) << 24) | ((x)&1))
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#define L3_SLS_HIBITS(x) (((x)&0x1f) << 18)
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#define L3_SLS_CONST(x) ((((x)&0x1f) << 18) | ((x)&0xffff))
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/* Delete this:
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#define L3_SLI_HIBITS(x) (((x)&0x7) << 18)
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*/
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#define L3_SLI_CONST(x) ((((x)&0x1f) << 18) | ((x)&0xffff))
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#define L3_SPLS_MODE(x) (((x)&0x5) << 12)
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#define L3_SBR_OP(x) (((x)&0x7) << 8)
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#define L3_OP1(x) (((x)&0x7) << 0)
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#define L3_OP2(x) (((x)&0x7) << 8)
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/* Sign-extend a value which is N bits long. */
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#define SIGN_EXT(value, bits) \
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((((int)(value)) << ((8 * sizeof(int)) - bits)) >> ((8 * sizeof(int)) - bits))
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/* Macros used to extract instruction fields. Not all fields have
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macros defined here, only those which are actually used. */
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#define X_RD(i) (((i) >> 23) & 0x1f)
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#define X_RS1(i) (((i) >> 18) & 0x1f)
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#define X_RS2(i) (((i) >> 11) & 0x1f)
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#define X_RS3(i) (((i) >> 3) & 0x1f)
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#define X_OP1(i) (((i) >> 0) & 0x07)
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#define X_OP2(i) (((i) >> 8) & 0x07)
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#define X_RI_OP(i) (((i) >> 28) & 0x07)
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#define X_RR_OP(i) X_OP2(i)
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#define X_RRM_OP(i) X_OP2(i)
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#define X_RRR_OP1(i) X_OP1(i)
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#define X_RRR_OP2(i) X_OP2(i)
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#define X_C10(i) ((i)&0x3ff)
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#define X_C16(i) ((i)&0xffff)
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#define X_C21(i) (((i)&0xffff) | (((i)&0x7c0000) >> 2))
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#define X_C25(i) ((i)&0x1fffffc)
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extern struct lanai_opcode lanai_opcodes[];
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extern const int bfd_lanai_num_opcodes;
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#define NUMOPCODES bfd_lanai_num_opcodes
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/* end of lanai.h */
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