b46e7bd4f2
* Print a warning if config for VM was NULL. * Add warning if register is not added to VM due to overlap. * Update PPC register profile. * Add vector and float registers. As well as some control and system registers. * Enable to write values 4bit registers. * PPC: Uplift most common instructions. * Print warning if reserved SPR instruction is encountered. * Update PC/LR addresses and add ca32 writes. * Write cache needs to get flushed so load and store tests don't share the same memory. * Add missing T/F branch mnemonics. * Add Move to/from CR/CR0-7 * Fix TA address calculation for branch instructions. * Add branch tests for branch mnemonics. * Add XNOP * NOP cache touch instructions. * Add undocumented ATTN instruction to the not_implemented group. * Add isel instruction. * Implement CRCLR, CRSET, CROR. * Add CNTLZ instructions. * Add mcrf instructions. * Add inacive test for cmpb. * Add Load bytes reverse instructions. * Add test and add address alignment to dcbz. * Add eqv test * Correct DIV and MUL operations * Add div tests. * Add tests and correct MT/MFXER * Remove register ca32, ov32 * Remove explici setting of cr register because QEMU does not do it. Otherwise we get a mismatch in the trace * Simplify carry set for add and sub. Sub instructions are exclusivly defined with addition. Hence no sub case needed. * Unify BD and fix branch instructions. Fix: Check the single bit not the cr reg * Document Conditional branches and replace NOPs with EMPTY * Add mulli instruction to double word instructions. * Fix ca set for shift instructions: * ca value had to be determined before the shift happened. The wrong ca value was calculated if the src and target reg were the same. * Replace NOP wit EMPTY. * Use MSB isntead of SLT. * Brought fixup of ADD and SUB instructions: The add and sub instructions had several issues which let to incorrect execution. * The carry was incorrectly if three add operations happened (only the last add were checked, not both). * The carry was incorrectly set if the src and target register matched. * Same applies for the CR bit. * It was too complex. Several local variables were introduced for this. * Set result in local var, since it would change if src and target reg are the same. * Remove MTMSR and MFMSR since it is too complex and untestable currently. * Use unsigned int for shift. Otherwise the 0x1c shift produces a runtime error since 0xf is int as default. * Fix mtxer: Only write flag bits. * Let NOT_IMPLEMENTED macro return NULL. * Mark st[wd]cx and l[wd]cx as not implemented. * Increase dcache_line_size to 128 bytes. * Fix cntlz for ppc32. m was set incorrectly, since it is 0 not 32 for 32bit cpus. * Fix isel: Use op.crx reg instead of imm. * Unify helper function names: Prependnig `ppc_` mark as IPI * Add more "Move to SPR" cases. * MULLI opeartes only on double word on 64bit CPUs. * Most registers are now assigned the control register type and no longer show up in the ar command. * Fix xor if dest and src registers match by saving result in local var. * Fix BE/LE issue for Load BRX instructions. * Fix shifts: Use only lower 6bits of n. * User Pure local variables for ROT macros. * Fix rldimi instructions. * n was not inverted. * more than 6 bits of n could be used * Add 32bit emulateme tests. * Add 64bit emulateme tests. * Determine lg(v) in inline function. * Calculate CR bit in C not in the VM. * Check if `~mask = 0` and skip mask calculation if yes. * Check for `sh == 0` and skip rotations where possible. * Remove `la` instruction. `la` is a mnemonic for `addi`. * Remove SPR instructions which are not supported by QEMU or not traced yet. For most set/read SPR instructions QEMU segfaults. In case of SPR 1 (xer), 8 (lr) and 9 (ctr) the assembler resolves them to their mnemonics (mtxer, mtlr etc.). This means the code here is never reached. To test the get_xer code MFXER was added again. The rz-tracetests will fail for this instructions (due to missing ca32, ov32). But this case is covert in an issue. |
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| .. | ||
| 6502 | ||
| arm32 | ||
| arm64 | ||
| avr | ||
| bf | ||
| ppc32 | ||
| ppc64 | ||