105 lines
3.1 KiB
C
105 lines
3.1 KiB
C
// SPDX-FileCopyrightText: 2016 bobby.smiles32 <bobby.smiles32@gmail.com>
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// SPDX-License-Identifier: LGPL-3.0-only
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// TODO: add assembler
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#include <rz_types.h>
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#include <rz_util.h>
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#include <rz_asm.h>
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#include <rz_lib.h>
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#include <stdarg.h>
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#include <stdio.h>
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#include "rsp_idec.h"
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static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
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rsp_instruction rz_instr;
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int i;
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/* all instructions are 32bit words */
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if (len < 4) {
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op->size = 0;
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return 0;
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}
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op->size = 4;
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ut32 iw = rz_read_ble32(buf, a->big_endian);
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rz_instr = rsp_instruction_decode(a->pc, iw);
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rz_strbuf_append(&op->buf_asm, rz_instr.mnemonic);
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for (i = 0; i < rz_instr.noperands; i++) {
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rz_strbuf_append(&op->buf_asm, (i == 0) ? " " : ", ");
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switch (rz_instr.operands[i].type) {
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case RSP_OPND_GP_REG:
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rz_strbuf_append(&op->buf_asm, rsp_gp_reg_soft_names[rz_instr.operands[i].u]);
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break;
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case RSP_OPND_OFFSET:
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case RSP_OPND_TARGET:
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rz_strbuf_appendf(&op->buf_asm, "0x%08" PFMT64x, rz_instr.operands[i].u);
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break;
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case RSP_OPND_ZIMM: {
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int shift = (rz_instr.operands[i].u & ~0xffff) ? 16 : 0;
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rz_strbuf_appendf(&op->buf_asm, "0x%04" PFMT64x,
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rz_instr.operands[i].u >> shift);
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} break;
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case RSP_OPND_SIMM:
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rz_strbuf_appendf(&op->buf_asm, "%s0x%04" PFMT64x,
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(rz_instr.operands[i].s < 0) ? "-" : "",
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(rz_instr.operands[i].s < 0) ? -rz_instr.operands[i].s : rz_instr.operands[i].s);
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break;
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case RSP_OPND_SHIFT_AMOUNT:
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rz_strbuf_appendf(&op->buf_asm, "%" PFMT64u, rz_instr.operands[i].u);
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break;
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case RSP_OPND_BASE_OFFSET:
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rz_strbuf_appendf(&op->buf_asm, "%s0x%04x(%s)",
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(rz_instr.operands[i].s < 0) ? "-" : "",
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(ut32)((rz_instr.operands[i].s < 0) ? -rz_instr.operands[i].s : rz_instr.operands[i].s),
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rsp_gp_reg_soft_names[rz_instr.operands[i].u]);
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break;
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case RSP_OPND_C0_REG:
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rz_strbuf_append(&op->buf_asm, rsp_c0_reg_soft_names[rz_instr.operands[i].u]);
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break;
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case RSP_OPND_C2_CREG:
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rz_strbuf_append(&op->buf_asm, rsp_c2_creg_names[rz_instr.operands[i].u]);
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break;
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case RSP_OPND_C2_ACCU:
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rz_strbuf_append(&op->buf_asm, rsp_c2_accu_names[rz_instr.operands[i].u]);
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break;
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case RSP_OPND_C2_VREG:
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rz_strbuf_append(&op->buf_asm, rsp_c2_vreg_names[rz_instr.operands[i].u]);
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break;
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case RSP_OPND_C2_VREG_BYTE:
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case RSP_OPND_C2_VREG_SCALAR:
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rz_strbuf_appendf(&op->buf_asm, "%s[%u]", rsp_c2_vreg_names[rz_instr.operands[i].u],
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(ut32)rz_instr.operands[i].s);
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break;
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case RSP_OPND_C2_VREG_ELEMENT:
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rz_strbuf_appendf(&op->buf_asm, "%s%s", rsp_c2_vreg_names[rz_instr.operands[i].u], rsp_c2_vreg_element_names[rz_instr.operands[i].s]);
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break;
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default: /* should not happend */
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rz_strbuf_append(&op->buf_asm, "???");
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break;
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}
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}
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return op->size;
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}
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RzAsmPlugin rz_asm_plugin_rsp = {
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.name = "rsp",
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.desc = "Reality Signal Processor",
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.arch = "rsp",
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.bits = 32,
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.endian = RZ_SYS_ENDIAN_BI, /* For conveniance, we don't force BIG endian but allow both to be used */
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.license = "LGPL3",
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.disassemble = &disassemble
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};
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#ifndef RZ_PLUGIN_INCORE
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RZ_API RzLibStruct rizin_plugin = {
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.type = RZ_LIB_TYPE_ASM,
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.data = &rz_asm_plugin_rsp,
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.version = RZ_VERSION
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};
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#endif
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