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FPU: Remove Unused isFpuEnable

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Unused on ARM, on RISC-V it is actually the final decision and not
a cache.

Signed-off-by: Indan Zupancic <indan@nul.nu>
This commit is contained in:
Indan Zupancic 2024-09-17 17:33:24 +01:00 committed by Gerwin Klein
parent a96982e576
commit 134ab60ae0
6 changed files with 5 additions and 38 deletions
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10
include/arch/arm/arch/32/mode/machine/fpu.h
View file

@ -34,8 +34,6 @@
#define FPEXC_DEX_BIT 29
#define FPEXC_FP2V_BIT 28
extern bool_t isFPUEnabledCached[CONFIG_MAX_NUM_NODES];
static void clearEnFPEXC(void)
{
word_t fpexc;
@ -167,13 +165,6 @@ static inline void enableFpu(void)
#else
setEnFPEXC();
#endif
isFPUEnabledCached[CURRENT_CPU_INDEX()] = true;
}
/* Check if FPU is enable */
static inline bool_t isFpuEnable(void)
{
return isFPUEnabledCached[CURRENT_CPU_INDEX()];
}
/* Load FPU state from memory into the FPU registers. */
@ -226,6 +217,5 @@ static inline void disableFpu(void)
} else {
clearEnFPEXC();
}
isFPUEnabledCached[CURRENT_CPU_INDEX()] = false;
}

15
include/arch/arm/arch/64/mode/machine/fpu.h
View file

@ -8,8 +8,6 @@
#include <mode/machine/registerset.h>
extern bool_t isFPUEnabledCached[CONFIG_MAX_NUM_NODES];
#ifdef CONFIG_HAVE_FPU
/* Store state in the FPU registers into memory. */
static inline void saveFpuState(tcb_t *thread)
@ -137,18 +135,6 @@ static inline void enableFpu(void)
} else {
enableFpuEL01();
}
isFPUEnabledCached[CURRENT_CPU_INDEX()] = true;
}
/* Current verification model does not include lazy FPU switching, i.e. it acts
* as if this function always returns true, so no FPU faults could be produced.
* In order to guard against deriving a contradiction, we don't allow the C
* parser to translate it. */
/** MODIFIES: */
/** DONT_TRANSLATE */
static inline bool_t isFpuEnable(void)
{
return isFPUEnabledCached[CURRENT_CPU_INDEX()];
}
#endif /* CONFIG_HAVE_FPU */
@ -160,6 +146,5 @@ static inline void disableFpu(void)
} else {
disableFpuEL0();
}
isFPUEnabledCached[CURRENT_CPU_INDEX()] = false;
}

8
include/arch/riscv/arch/machine/fpu.h
View file

@ -31,7 +31,7 @@ static inline void set_fs_off(void)
#endif
extern bool_t isFPUEnabledCached[CONFIG_MAX_NUM_NODES];
extern bool_t isFPUEnabled[CONFIG_MAX_NUM_NODES];
static inline void set_fs_clean(void)
{
@ -154,17 +154,17 @@ static inline void loadFpuState(const tcb_t *thread)
static inline void enableFpu(void)
{
isFPUEnabledCached[CURRENT_CPU_INDEX()] = true;
isFPUEnabled[CURRENT_CPU_INDEX()] = true;
}
static inline void disableFpu(void)
{
isFPUEnabledCached[CURRENT_CPU_INDEX()] = false;
isFPUEnabled[CURRENT_CPU_INDEX()] = false;
}
static inline bool_t isFpuEnable(void)
{
return isFPUEnabledCached[CURRENT_CPU_INDEX()];
return isFPUEnabled[CURRENT_CPU_INDEX()];
}
static inline void set_tcb_fs_state(tcb_t *tcb, bool_t enabled)

6
src/arch/arm/32/machine/fpu.c
View file

@ -10,12 +10,6 @@
#include <config.h>
#include <util.h>
/* We cache the following value to avoid reading the coprocessor when isFpuEnable()
* is called. enableFpu() and disableFpu(), the value is set to cache/reflect the
* actual HW FPU enable/disable state.
*/
bool_t isFPUEnabledCached[CONFIG_MAX_NUM_NODES];
/*
* The following function checks if the subarchitecture support asynchronous exceptions
*/

2
src/arch/arm/64/machine/fpu.c
View file

@ -8,8 +8,6 @@
#include <arch/machine/fpu.h>
#include <mode/model/statedata.h>
bool_t isFPUEnabledCached[CONFIG_MAX_NUM_NODES];
#ifdef CONFIG_HAVE_FPU
/* Initialise the FP/SIMD for this machine. */
BOOT_CODE bool_t fpsimd_init(void)

2
src/arch/riscv/machine/fpu.c
View file

@ -7,5 +7,5 @@
#ifdef CONFIG_HAVE_FPU
#include <arch/machine/fpu.h>
bool_t isFPUEnabledCached[CONFIG_MAX_NUM_NODES];
bool_t isFPUEnabled[CONFIG_MAX_NUM_NODES];
#endif