risc-v: improve PLIC driver API and documentation
- describe PLIC behavior and corner cases. - provide a common header file for the API. - add a dummy PLIC driver for spike. Signed-off-by: Axel Heider <axel.heider@hensoldt-cyber.de>
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Axel Heider
Kent McLeod
parent
624786b95f
commit
1400a8a8a2
4 changed files with 148 additions and 42 deletions
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/*
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* Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
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* Copyright 2021, HENSOLDT Cyber
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*
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* SPDX-License-Identifier: GPL-2.0-only
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*/
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#pragma once
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#include <config.h>
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#include <types.h>
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/*
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* RISC-V defines a Platform-level interrupt controller (PLIC) (priv-1.10).
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* It is responsible for managing global interrupts in a RISC-V system.
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* The "RISC-V Instruction Set Manual Volume II: Privileged Architecture" V1.10
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* defines a platform-level interrupt controller (PLIC), that manages global
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* interrupt on a RISC-V platform. A PLIC takes multiple interrupt sources,
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* usually the platform peripherals, and delivers them to different hart
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* contexts depending on the interrupt routing configuration. A hart is a
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* logical CPU core, a hart context is a privilege level on a given hart,
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* usually M-Mode or S-Mode.
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*
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* A PLIC takes multiple interrupt sources from external devices and delivers
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* them to different HART contexts depending on per IRQ configuration registers.
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* A HART context is a given privilege level on a given HART. If an IRQ is pending
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* for a particular HART context, the PLIC will raise an interrupt on that HART context's
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* External interrupt pending(EIP) pin and trigger an interrupt. The HART can then claim
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* the IRQ message by communicating with the PLIC where it will receive the highest
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* priority pending interrupt. The PLIC will deassert the EIP pin when there are
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* no more pending interrupts for that HART. When the HART has finished processing
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* the IRQ it completes the claim by notifying the PLIC. Until an IRQ claim has
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* completed, the PLIC won't generate futher interrupts for that IRQ. In multicore
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* systems, if an IRQ is routed to multiple HARTs, the first HART to claim the IRQ
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* gets to process the IRQ and subsequent HARTs won't receive a claim for the same IRQ.
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* If an interrupt is pending for a particular hart context, the PLIC will
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* assert the hart context's external interrupt line. The hart can then issue
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* an interrupt claim to the PLIC, in response it will receive the pending
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* interrupt with the highest priority. In multicore systems, if an interrupt is
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* routed to multiple harts, the first hart to claim it gets to process it and
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* subsequent harts won't see it. Upon claiming, the PLIC will de-assert a hart
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* context's external interrupt line, even if there are more pending interrupt.
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* When a hart has finished processing a claimed interrupt, it notifies the
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* PLIC about the completion. The PLIC will assert the hart context's external
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* interrupt line if there are more pending interrupts.
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*
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* We require each platform to provide the following functions:
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* irq_t plic_get_claim(void): If called when an IRQ is pending, returns
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* the pending priority and starts a claim process. Will return irqInvalid
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* if no IRQs are pending.
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* void plic_complete_claim(irq_t irq): Complete a claim process for an
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* interrupt.
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* void plic_mask_irq(bool_t disable, irq_t irq): Disables or enables an
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* IRQ at the PLIC.
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* void plic_irq_set_trigger(irq_t irq, bool_t edge_triggered): Configure
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* an IRQ source on the PLIC to be edge or level triggered. This function does
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* not need to be implemented if the PLIC doesn't support configuring this.
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* void plic_init_controller(void): Perform PLIC initialisation during boot.
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* The RISC-V specification is not clear how interrupt priorities affect
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* asserting a hart context's external interrupt line. The PLIC is supposed to
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* deassert the line upon interrupt claiming. but could asserted it again if an
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* interrupt of a higher priority arrives, even if the current claim has no been
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* completed. This allows interrupt nesting. However, seL4 does not support this
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* and cannot be interrupted when running in kernel mode. To achieve this, it
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* keeps the S-Mode hart context's external interrupts masked until leaving to
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* user space. However, great care must be taken if interrupt priorities are not
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* implemented in the PLIC and the interrupt claim completion does not happen
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* within the kernel's interrupt trap handling. If completion is done when the
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* user mode ISR ack's the interrupt, the user mode driver that implements the
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* ISR can simply block all other platform interrupts by not doing the ack.
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* Luckily, this will not affect the timer used for the preemptive scheduler,
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* because RISC-V has a dedicated timer interrupt that is separate from the
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* external interrupt.
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*
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*
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* This file defines the seL4 kernel's internal API for PLIC access that must be
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* implemented by platform specific PLIC drivers.
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* The implementation here are
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* used on the 'spike' platform, which is just a RISC-V ISA reference
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* implementation that does not have a PLIC to trigger external interrupts.
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*/
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static inline irq_t plic_get_claim(void)
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{
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return irqInvalid;
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}
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static inline void plic_complete_claim(irq_t irq)
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{
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}
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/*
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* This function is called when an interrupt is pending. It claims an interrupt
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* from the PLIC and returns it. If no interrupt could be claimed 'irqInvalid'
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* is returned.
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*
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* @return interrupt number or irqInvalid.
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*/
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static inline irq_t plic_get_claim(void);
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/*
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* This function is called to complete a claim process for an interrupt.
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*
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* @param[in] irq interrupt to complete.
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*/
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static inline void plic_complete_claim(irq_t irq);
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/*
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* This function is called to mask (disable) or unmasks (enable) an interrupt in
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* the PLIC.
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*
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* @param[in] disable True to mask/disable, False to unmask/enable.
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* @param[in] irq interrupt to mask/unmask.
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*/
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static inline void plic_mask_irq(bool_t disable, irq_t irq);
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static inline void plic_mask_irq(bool_t disable, irq_t irq)
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{
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}
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#ifdef HAVE_SET_TRIGGER
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/*
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* If HAVE_SET_TRIGGER is defined, this function is called to configure an
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* interrupt source on the PLIC as edge or level triggered. By default all
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* interrupts should be configures to be edge triggered.
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*
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* @param[in] irq interrupt to set trigger mode for.
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* @param[in] edge_triggered True for edge triggered, False for level
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* triggered.
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*/
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static inline void plic_irq_set_trigger(irq_t irq, bool_t edge_triggered);
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#endif
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#endif /* HAVE_SET_TRIGGER */
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static inline void plic_init_controller(void)
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{
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}
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/*
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* This function is called during the boot process to perform hart specific
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* PLIC initialisation. It is called as part of the core local initialisation
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* process and runs before plic_init_controller() is called.
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*/
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static inline void plic_init_hart(void);
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/*
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* This function is called during the boot process to perform platform specific
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* PLIC initialisation. It is called as part of the platform specific
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* initialisation pprocess and runs after the core specific plic_init_hart() was
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* called. In SMP configurations this is called before the secondary cores are
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* released to start their boot process.
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*/
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static inline void plic_init_controller(void);
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@ -1,16 +1,18 @@
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/*
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* Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
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* Copyright 2021, HENSOLDT Cyber
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*
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* SPDX-License-Identifier: GPL-2.0-only
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*/
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#pragma once
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/* tell the kernel we have the set trigger feature */
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#define HAVE_SET_TRIGGER 1
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#include <plat/machine/devices_gen.h>
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#include <arch/model/smp.h>
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#include <arch/machine/plic.h>
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/* The memory map is based on the PLIC section in
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* https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
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52
include/drivers/irq/riscv_plic_dummy.h
Normal file
52
include/drivers/irq/riscv_plic_dummy.h
Normal file
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@ -0,0 +1,52 @@
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/*
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* Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
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* Copyright 2021, HENSOLDT Cyber
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*
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* SPDX-License-Identifier: GPL-2.0-only
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*
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* A dummy PLIC driver for platforms like spike that do not implement a PLIC.
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* This can be taken as a template for platform specific PLIC drivers.
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*/
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#pragma once
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/* Since this is a template, it has a dummy implementation for the trigger API
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* function plic_irq_set_trigger().
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*/
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#define HAVE_SET_TRIGGER 1
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#include <arch/machine/plic.h>
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static inline irq_t plic_get_claim(void)
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{
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printf("no PLIC present, can't claim any interrupt\n");
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return irqInvalid;
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}
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static inline void plic_complete_claim(irq_t irq)
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{
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printf("no PLIC present, can't complete claim for interrupt %d\n",
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(int)irq);
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}
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static inline void plic_mask_irq(bool_t disable, irq_t irq)
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{
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printf("no PLIC present, can't %s interrupt %d\n",
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disable ? "mask" : "unmask", (int)irq);
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}
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static inline void plic_irq_set_trigger(irq_t irq, bool_t edge_triggered)
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{
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printf("no PLIC present, can't set interrupt %d to %s triggered\n",
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(int)irq, edge_triggered ? "edge" : "level");
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}
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static inline void plic_init_hart(void)
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{
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printf("no PLIC present, skip hart specific initialisation\n");
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}
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static inline void plic_init_controller(void)
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{
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printf("no PLIC present, skip platform specific initialisation\n");
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}
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@ -1,6 +1,7 @@
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#
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# Copyright 2020, DornerWorks
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# Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
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# Copyright 2021, HENSOLDT Cyber
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#
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# SPDX-License-Identifier: GPL-2.0-only
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#
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@ -27,7 +28,7 @@ if(KernelPlatformSpike)
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endif()
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declare_default_headers(
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TIMER_FREQUENCY 10000000 PLIC_MAX_NUM_INT 0
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INTERRUPT_CONTROLLER arch/machine/plic.h
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INTERRUPT_CONTROLLER drivers/irq/riscv_plic_dummy.h
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)
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else()
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unset(KernelPlatformFirstHartID CACHE)
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