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Aarch32, FPU: Remove FPEXC DEX and EX checks

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According to Arm documentation, the exception-handling routine
needs to zero the following bits in FPEXC:

DEX, IDF, IXF, UFF, OFF, DZF and IOF

In seL4, the user space fault handler should do this, as the kernel
doesn't know when user space is done handling the FPU trap.

In case of virtualisation, the guest kernel should clear these bits.

Now that the seL4 kernel doesn't handle FPU traps itself any more,
user space can handle asynchronous traps if it wants to.

Signed-off-by: Indan Zupancic <indan@nul.nu>
This commit is contained in:
Indan Zupancic 2025-04-24 22:21:25 +01:00 committed by Gerwin Klein
parent 77f5fab0a0
commit 180eb4db78
1 changed files with 0 additions and 14 deletions
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14
include/arch/arm/arch/32/mode/machine/fpu.h
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@ -84,17 +84,6 @@ static inline void saveFpuState(tcb_t *thread)
/* Fetch FPEXC. */
VMRS(FPEXC, fpexc);
#if defined(CONFIG_ARM_CORTEX_A7) || defined(CONFIG_ARM_CORTEX_A9)
/*
* Reset DEX bit to 0 in case a subarchitecture sets it.
* For example, Cortex-A7/A9 set this bit on deprecated vector VFP operations.
*/
if (unlikely(fpexc & BIT(FPEXC_DEX_BIT))) {
fpexc &= ~BIT(FPEXC_DEX_BIT);
VMSR(FPEXC, fpexc);
}
#endif
dest->fpexc = fpexc;
if (config_set(CONFIG_ARM_HYPERVISOR_SUPPORT)) {
@ -102,9 +91,6 @@ static inline void saveFpuState(tcb_t *thread)
setEnFPEXC();
}
/* We don't support asynchronous exceptions */
assert((dest->fpexc & BIT(FPEXC_EX_BIT)) == 0);
if (isFPUD32SupportedCached) {
register word_t regs_d16_d31 asm("ip") = (word_t) &dest->fpregs[16];
asm volatile(