From 1f2f6b98bb2063017d91edb47cd1431ecfa818df Mon Sep 17 00:00:00 2001 From: Adrian Danis Date: Mon, 29 May 2017 17:00:34 +1000 Subject: [PATCH] Use CONFIG_ variables instead of configuration definitions --- include/arch/arm/arch/32/mode/machine.h | 18 +++++++++--------- .../arch/arm/arch/32/mode/machine/hardware.h | 10 +++++----- .../arch/arm/arch/64/mode/machine/hardware.h | 4 ++-- include/plat/exynos5/plat/machine.h | 4 ++-- include/plat/exynos5/plat/machine/devices.h | 4 ++-- src/arch/arm/armv/armv8-a/32/machine_asm.S | 3 ++- 6 files changed, 22 insertions(+), 21 deletions(-) diff --git a/include/arch/arm/arch/32/mode/machine.h b/include/arch/arm/arch/32/mode/machine.h index 9da54aa9e..0a916e8ee 100644 --- a/include/arch/arm/arch/32/mode/machine.h +++ b/include/arch/arm/arch/32/mode/machine.h @@ -254,7 +254,7 @@ void lockTLBEntry(vptr_t vaddr); static inline void cleanByVA(vptr_t vaddr, paddr_t paddr) { -#ifdef ARM_CORTEX_A8 +#ifdef CONFIG_ARM_CORTEX_A8 /* Erratum 586324 -- perform a dummy cached load before flushing. */ asm volatile("ldr r0, [sp]" : : : "r0"); /* Erratum 586320 -- clean twice with interrupts disabled. */ @@ -270,21 +270,21 @@ static inline void cleanByVA(vptr_t vaddr, paddr_t paddr) /* D-Cache clean to PoU (L2 cache) (v6/v7 common) */ static inline void cleanByVA_PoU(vptr_t vaddr, paddr_t paddr) { -#ifdef ARM_CORTEX_A8 +#ifdef CONFIG_ARM_CORTEX_A8 /* Erratum 586324 -- perform a dummy cached load before flushing. */ asm volatile("ldr r0, [sp]" : : : "r0"); asm volatile("mcr p15, 0, %0, c7, c11, 1" : : "r"(vaddr)); #elif defined(CONFIG_ARCH_ARM_V6) /* V6 doesn't distinguish PoU and PoC, so use the basic flush. */ asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr)); -#elif defined(PLAT_EXYNOS5) +#elif defined(CONFIG_PLAT_EXYNOS5) /* Flush to coherency for table walks... Why? */ asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr)); -#elif defined(PLAT_IMX7) +#elif defined(CONFIG_PLAT_IMX7) asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr)); #elif defined(CONFIG_PLAT_TK1) asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr)); -#elif defined(ARM_CORTEX_A53) +#elif defined(CONFIG_ARM_CORTEX_A53) asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr)); #else asm volatile("mcr p15, 0, %0, c7, c11, 1" : : "r"(vaddr)); @@ -296,7 +296,7 @@ static inline void cleanByVA_PoU(vptr_t vaddr, paddr_t paddr) /* D-Cache invalidate to PoC (v6/v7 common) */ static inline void invalidateByVA(vptr_t vaddr, paddr_t paddr) { -#ifdef ARM_CORTEX_A8 +#ifdef CONFIG_ARM_CORTEX_A8 /* Erratum 586324 -- perform a dummy cached load before flushing. */ asm volatile("ldr r0, [sp]" : : : "r0"); asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r"(vaddr)); @@ -309,7 +309,7 @@ static inline void invalidateByVA(vptr_t vaddr, paddr_t paddr) /* I-Cache invalidate to PoU (L2 cache) (v6/v7 common) */ static inline void invalidateByVA_I(vptr_t vaddr, paddr_t paddr) { -#ifdef ARM_CORTEX_A8 +#ifdef CONFIG_ARM_CORTEX_A8 /* On A8, we just invalidate the lot. */ asm volatile("mcr p15, 0, %0, c7, c5, 0" : : "r"(0)); #else @@ -321,7 +321,7 @@ static inline void invalidateByVA_I(vptr_t vaddr, paddr_t paddr) /* I-Cache invalidate all to PoU (L2 cache) (v6/v7 common) */ static inline void invalidate_I_PoU(void) { -#ifdef ARM_CORTEX_A8 +#ifdef CONFIG_ARM_CORTEX_A8 /* Erratum 586324 -- perform a dummy cached load before flushing. */ asm volatile("ldr r0, [sp]" : : : "r0"); #endif @@ -332,7 +332,7 @@ static inline void invalidate_I_PoU(void) /* D-Cache clean & invalidate to PoC (v6/v7 common) */ static inline void cleanInvalByVA(vptr_t vaddr, paddr_t paddr) { -#ifdef ARM_CORTEX_A8 +#ifdef CONFIG_ARM_CORTEX_A8 /* Erratum 586324 -- perform a dummy cached load before flushing. */ asm volatile("ldr r0, [sp]" : : : "r0"); /* Erratum 586320 -- clean twice with interrupts disabled. */ diff --git a/include/arch/arm/arch/32/mode/machine/hardware.h b/include/arch/arm/arch/32/mode/machine/hardware.h index a9fdab2cf..b6bfed42e 100644 --- a/include/arch/arm/arch/32/mode/machine/hardware.h +++ b/include/arch/arm/arch/32/mode/machine/hardware.h @@ -21,19 +21,19 @@ #if defined(CONFIG_ARM1136JF_S) #define L1_CACHE_LINE_SIZE_BITS 5 /* 32 bytes */ -#elif defined(ARM_CORTEX_A8) +#elif defined(CONFIG_ARM_CORTEX_A8) #define L1_CACHE_LINE_SIZE_BITS 6 /* 64 bytes */ -#elif defined(ARM_CORTEX_A9) +#elif defined(CONFIG_ARM_CORTEX_A9) #define L1_CACHE_LINE_SIZE_BITS 5 /* 32 bytes */ -#elif defined(ARM_CORTEX_A7) +#elif defined(CONFIG_ARM_CORTEX_A7) #define L1_CACHE_LINE_SIZE_BITS 6 /* 64 bytes */ -#elif defined(ARM_CORTEX_A15) +#elif defined(CONFIG_ARM_CORTEX_A15) #define L1_CACHE_LINE_SIZE_BITS 6 /* 64 bytes */ -#elif defined(ARM_CORTEX_A53) +#elif defined(CONFIG_ARM_CORTEX_A53) #define L1_CACHE_LINE_SIZE_BITS 6 /* 64 bytes */ #endif diff --git a/include/arch/arm/arch/64/mode/machine/hardware.h b/include/arch/arm/arch/64/mode/machine/hardware.h index 80d8bf23a..5437ad3ac 100644 --- a/include/arch/arm/arch/64/mode/machine/hardware.h +++ b/include/arch/arm/arch/64/mode/machine/hardware.h @@ -18,11 +18,11 @@ #define PAGE_BITS seL4_PageBits -#if defined(ARM_CORTEX_A53) +#if defined(CONFIG_ARM_CORTEX_A53) #define L1_CACHE_LINE_SIZE_BITS 6 /* 64 bytes */ #endif -#if defined(ARM_CORTEX_A57) +#if defined(CONFIG_ARM_CORTEX_A57) #define L1_CACHE_LINE_SIZE_BITS 6 /* 64 bytes */ #endif diff --git a/include/plat/exynos5/plat/machine.h b/include/plat/exynos5/plat/machine.h index 435998048..bed8181fe 100644 --- a/include/plat/exynos5/plat/machine.h +++ b/include/plat/exynos5/plat/machine.h @@ -81,9 +81,9 @@ enum IRQConstants { INTERRUPT_INTG30 = 62, INTERRUPT_INTG31 = 63, INTERRUPT_EINT16_31 = 64, -#if defined(PLAT_EXYNOS5250) +#if defined(CONFIG_PLAT_EXYNOS5250) INTERRUPT_MDMA0_CORE = 65, -#elif defined(PLAT_EXYNOS5410) +#elif defined(CONFIG_PLAT_EXYNOS5410) INTERRUPT_TMU_CPU0 = 65, #else #endif diff --git a/include/plat/exynos5/plat/machine/devices.h b/include/plat/exynos5/plat/machine/devices.h index 5571f32db..d018fb95b 100644 --- a/include/plat/exynos5/plat/machine/devices.h +++ b/include/plat/exynos5/plat/machine/devices.h @@ -259,13 +259,13 @@ #define AUDSS_PADDR 0x03810000 /* SoC specific devices */ -#if defined(PLAT_EXYNOS5250) /* Arndale */ +#if defined(CONFIG_PLAT_EXYNOS5250) /* Arndale */ #define GPIO_LEFT_PADDR 0x11400000 #define GPIO_RIGHT_PADDR 0x13400000 #define C2C_GPIO_PADDR 0x10D10000 #define AUDIO_GPIO_PADDR 0x03860000 -#elif defined(PLAT_EXYNOS54XX) /* Odroid XU and XU3 */ +#elif defined(CONFIG_PLAT_EXYNOS54XX) /* Odroid XU and XU3 */ #define GPIO_LEFT_PADDR 0x14000000 #define GPIO_RIGHT_PADDR 0x13400000 #define C2C_GPIO_PADDR 0x10D10000 diff --git a/src/arch/arm/armv/armv8-a/32/machine_asm.S b/src/arch/arm/armv/armv8-a/32/machine_asm.S index b79630693..18777114f 100644 --- a/src/arch/arm/armv/armv8-a/32/machine_asm.S +++ b/src/arch/arm/armv/armv8-a/32/machine_asm.S @@ -8,9 +8,10 @@ * @TAG(GD_GPL) */ +#include #include -#if defined(ARM_CORTEX_A53) +#if defined(CONFIG_ARM_CORTEX_A53) /* A53 hardware does not support TLB locking */ BEGIN_FUNC(lockTLBEntry)