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tools: add risc-v dtb interrupt parsing

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Co-authored-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
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Gerwin Klein 2021-08-23 17:56:36 +10:00 committed by Gerwin Klein
parent 3398c01ee9
commit 2296484665
1 changed files with 1 additions and 0 deletions
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tools/hardware/irq.py
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@ -186,6 +186,7 @@ CONTROLLERS = {
'ti,am33xx-intc': RawIrqController,
'ti,omap3-intc': RawIrqController,
'riscv,cpu-intc': RawIrqController,
'riscv,plic0': RawIrqController,
}