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riscv: Add support for Rocketchip SoC

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Support Rocketchip SoC maps to Xilinx ZC706 board and ZCU102 board
This commit is contained in:
Siwei Zhuang 2019-11-26 17:49:46 +11:00
parent 0d1814e5a8
commit 249bcdab63
4 changed files with 174 additions and 13 deletions
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20
libsel4/sel4_plat_include/rocketchip/sel4/plat/api/constants.h Normal file
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/*
* Copyright 2019, Data61
* Commonwealth Scientific and Industrial Research Organisation (CSIRO)
* ABN 41 687 119 230.
*
* This software may be distributed and modified according to the terms of
* the BSD 2-Clause license. Note that NO WARRANTY is provided.
* See "LICENSE_BSD2.txt" for details.
*
* @TAG(DATA61_BSD)
*/
#ifndef __LIBSEL4_SEL4_PLAT_API_CONSTANTS_H_
#define __LIBSEL4_SEL4_PLAT_API_CONSTANTS_H_
#ifdef HAVE_AUTOCONF
#include <autoconf.h>
#endif
#endif /* __LIBSEL4_SEL4_PLAT_API_CONSTANTS_H_ */

28
src/plat/rocketchip/config.cmake Normal file
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#
# Copyright 2019, Data61
# Commonwealth Scientific and Industrial Research Organisation (CSIRO)
# ABN 41 687 119 230.
#
# This software may be distributed and modified according to the terms of
# the GNU General Public License version 2. Note that NO WARRANTY is provided.
# See "LICENSE_GPLv2.txt" for details.
#
# @TAG(DATA61_GPL)
#
cmake_minimum_required(VERSION 3.7.2)
declare_platform(rocketchip KernelPlatformRocketchip PLAT_ROCKETCHIP KernelArchRiscV)
if(KernelPlatformRocketchip)
declare_seL4_arch(riscv64)
config_set(KernelRiscVPlatform RISCV_PLAT "rocketchip")
config_set(KernelPlatformFirstHartID FIRST_HART_ID 0)
list(APPEND KernelDTSList "tools/dts/rocketchip.dts")
declare_default_headers(
TIMER_FREQUENCY 10000000llu PLIC_MAX_NUM_INT 0
INTERRUPT_CONTROLLER arch/machine/plic.h
)
else()
unset(KernelPlatformFirstHartID CACHE)
endif()

13
src/plat/spike/instance/rocket-chip/config.cmake
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#
# Copyright 2018, DornerWorks
#
# This software may be distributed and modified according to the terms of
# the GNU General Public License version 2. Note that NO WARRANTY is provided.
# See "LICENSE_GPLv2.txt" for details.
#
# @TAG(DORNERWORKS_GPL)
#
if(KernelPlatformSpikeRocketChip)
set(KernelPlatformSpikeClockFrequency 250000)
endif()

126
tools/dts/rocketchip.dts Normal file
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/* @TAG(OTHER_GPL) */
/*
* Copyright (c) 2012-2014, The Regents of the University of California
* (Regents). All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Regents nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
* SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
* OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
* HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
* MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
*/
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-dev";
model = "freechips,rocketchip-unknown";
chosen {
};
L13: cpus {
#address-cells = <1>;
#size-cells = <0>;
L5: cpu@0 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <16384>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L6>;
reg = <0>;
riscv,isa = "rv64imafdc";
status = "okay";
timebase-frequency = <1000000>;
tlb-split;
L3: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
L6: memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
L12: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
ranges;
L10: blkdev-controller@10015000 {
compatible = "ucbbar,blkdev";
interrupt-parent = <&L0>;
interrupts = <3>;
reg = <0x10015000 0x1000>;
reg-names = "control";
};
L1: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L3 3 &L3 7>;
reg = <0x2000000 0x10000>;
reg-names = "control";
};
L2: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
interrupts-extended = <&L3 65535>;
reg = <0x0 0x1000>;
reg-names = "control";
};
L7: error-device@3000 {
compatible = "sifive,error0";
reg = <0x3000 0x1000>;
reg-names = "mem";
};
L9: external-interrupts {
interrupt-parent = <&L0>;
interrupts = <1 2>;
};
L0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&L3 11 &L3 9>;
reg = <0xc000000 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <3>;
};
L8: rom@10000 {
compatible = "sifive,rom0";
reg = <0x10000 0x10000>;
reg-names = "mem";
};
};
htif {
compatible = "ucb,htif0";
};
};