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riscv: Add FPU state in TCB

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Add FPU state storage in TCB and increase TCB size bits when FPU
is enabled.

Signed-off-by: Yanyan Shen <yanyan.shen@data61.csiro.au>
This commit is contained in:
Yanyan Shen 2019-11-18 16:55:31 +08:00 committed by Siwei Zhuang
parent b8aa983e31
commit 4006310e68
2 changed files with 26 additions and 0 deletions
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22
include/arch/riscv/arch/machine/registerset.h
View file

@ -89,8 +89,30 @@ extern const register_t msgRegisters[] VISIBLE;
extern const register_t frameRegisters[] VISIBLE;
extern const register_t gpRegisters[] VISIBLE;
#ifdef CONFIG_HAVE_FPU
#define RISCV_NUM_FP_REGS 32
#if defined(CONFIG_RISCV_EXT_D)
typedef uint64_t fp_reg_t;
#elif defined(CONFIG_RISCV_EXT_F)
typedef uint32_t fp_reg_t;
#else
#error Unknown RISCV FPU extension
#endif
typedef struct user_fpu_state {
fp_reg_t regs[RISCV_NUM_FP_REGS];
uint32_t fcsr;
} user_fpu_state_t;
#endif
struct user_context {
word_t registers[n_contextRegisters];
#ifdef CONFIG_HAVE_FPU
user_fpu_state_t fpuState;
#endif
};
typedef struct user_context user_context_t;

4
libsel4/sel4_arch_include/riscv64/sel4/sel4_arch/constants.h
View file

@ -24,7 +24,11 @@
#endif
#define seL4_EndpointBits 4
#define seL4_IPCBufferSizeBits 10
#ifdef CONFIG_HAVE_FPU
#define seL4_TCBBits 11
#else
#define seL4_TCBBits 10
#endif
/* Sv39/Sv48 pages/ptes sizes */
#define seL4_PageTableEntryBits 3