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aarch32: Fix d-cache flush

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It seems all Cortex-A7, Cortex-A15, Cortex-A53 boards require to
flush to coherency in order to get it work.
It is a temporary fix, and we will keep track on this issue.

Signed-off-by: Luca (Wei) Chen <wei@cvluca.com>
This commit is contained in:
Luca (Wei) Chen 2021-11-16 10:47:37 +08:00 committed by Gerwin Klein
parent c036e6c676
commit 4480ac9648
1 changed files with 5 additions and 7 deletions
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12
include/arch/arm/arch/32/mode/machine.h
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@ -366,15 +366,13 @@ static inline void cleanByVA_PoU(vptr_t vaddr, paddr_t paddr)
/* Erratum 586324 -- perform a dummy cached load before flushing. */
asm volatile("ldr r0, [sp]" : : : "r0");
asm volatile("mcr p15, 0, %0, c7, c11, 1" : : "r"(vaddr));
#elif defined(CONFIG_PLAT_EXYNOS5)
#elif defined(CONFIG_ARCH_ARM_V6)
/* V6 doesn't distinguish PoU and PoC, so use the basic flush. */
asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
#elif defined(CONFIG_ARM_CORTEX_A7) || defined(CONFIG_ARM_CORTEX_A15) || \
defined(CONFIG_ARM_CORTEX_A53)
/* Flush to coherency for table walks... Why? */
asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
#elif defined(CONFIG_PLAT_IMX7)
asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
#elif defined(CONFIG_PLAT_TK1)
asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
#elif defined(CONFIG_ARM_CORTEX_A53)
asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
#else
asm volatile("mcr p15, 0, %0, c7, c11, 1" : : "r"(vaddr));
#endif