add seL4_BenchmarkFlushCaches() for arm and ia32

Available when CONFIG_ENABLE_BENCHMARKS is set, flushes caches for
running cold-cache benchmarks

include/arch/arm/arch/32/mode/machine.h

@@ -354,4 +354,6 @@ static inline void setACTLR(word_t actlr)
     asm volatile ("mcr p15, 0, %0, c1, c0, 1" :: "r"(actlr));
 }
 
+void arch_clean_invalidate_caches(void);
+
 #endif /* __ARCH_MACHINE_32_H */

include/arch/arm/arch/machine/l2c_310.h

@@ -21,6 +21,8 @@
 /** MODIFIES: [*] */
 void initL2Cache(void);
 
+/** MODIFIES: [*] */
+void plat_cleanInvalidateCache(void);
 /** MODIFIES: [*] */
 void plat_cleanCache(void);
 /** MODIFIES: [*] */

include/arch/x86/arch/32/mode/machine.h

@@ -117,6 +117,12 @@ static inline void ia32_wbinvd(void)
     asm volatile("wbinvd" ::: "memory");
 }
 
+static inline void
+arch_clean_invalidate_caches(void)
+{
+    ia32_wbinvd();
+}
+
 /* GDT installation */
 void ia32_install_gdt(gdt_idt_ptr_t* gdt_idt_ptr);
 

libsel4/include/api/syscall.xml

@@ -38,6 +38,7 @@
             <syscall name="DebugRun"/>
         </config>
         <config condition="defined CONFIG_ENABLE_BENCHMARKS">
+            <syscall name="BenchmarkFlushCaches" />
             <syscall name="BenchmarkResetLog" />
             <syscall name="BenchmarkFinalizeLog"  />
             <syscall name="BenchmarkSetLogBuffer"  />

libsel4/sel4_arch_include/aarch32/sel4/sel4_arch/syscalls.h

@@ -576,6 +576,13 @@ seL4_BenchmarkNullSyscall(void)
     asm volatile("" ::: "memory");
 }
 
+static inline void
+seL4_BenchmarkFlushCaches(void)
+{
+    arm_sys_null(seL4_SysBenchmarkFlushCaches);
+    asm volatile("" ::: "memory");
+}
+
 #ifdef CONFIG_BENCHMARK_TRACK_UTILISATION
 static inline void
 seL4_BenchmarkGetThreadUtilisation(seL4_Word tcp_cptr)

libsel4/sel4_arch_include/ia32/sel4/sel4_arch/syscalls.h

@@ -610,6 +610,13 @@ seL4_BenchmarkNullSyscall(void)
     asm volatile("" :::"%esi", "%edi", "memory");
 }
 
+static inline void
+seL4_BenchmarkFlushCaches(void)
+{
+    x86_sys_null(seL4_SysBenchmarkFlushCaches);
+    asm volatile("" :::"%esi", "%edi", "memory");
+}
+
 #ifdef CONFIG_BENCHMARK_TRACK_UTILISATION
 static inline void
 seL4_BenchmarkGetThreadUtilisation(seL4_Word tcb_cptr)

src/api/syscall.c

@@ -119,7 +119,10 @@ handleUnknownSyscall(word_t w)
 #endif
 
 #ifdef CONFIG_ENABLE_BENCHMARKS
-    if (w == SysBenchmarkResetLog) {
+    if (w == SysBenchmarkFlushCaches) {
+        arch_clean_invalidate_caches();
+        return EXCEPTION_NONE;
+    } else if (w == SysBenchmarkResetLog) {
 #ifdef CONFIG_BENCHMARK_USE_KERNEL_LOG_BUFFER
         if (ksUserLogBuffer == 0) {
             userError("A user-level buffer has to be set before resetting benchmark.\

src/arch/arm/machine/cache.c

@@ -11,6 +11,7 @@
 #include <api/types.h>
 #include <arch/machine.h>
 #include <arch/machine/hardware.h>
+#include <arch/machine/l2c_310.h>
 
 #define LINE_START(a) ROUND_DOWN(a, L1_CACHE_LINE_SIZE_BITS)
 #define LINE_INDEX(a) (LINE_START(a)>>L1_CACHE_LINE_SIZE_BITS)
@@ -184,3 +185,12 @@ cleanInvalidateL1Caches(void)
     invalidate_I_PoU();
     dsb();
 }
+
+void
+arch_clean_invalidate_caches(void)
+{
+     cleanCaches_PoU();
+     plat_cleanInvalidateCache();
+     cleanInvalidateL1Caches();
+     isb();
+}

src/arch/arm/machine/l2c_310.c

@@ -361,6 +361,17 @@ static inline void L2_cacheSync(void)
     while (l2cc->maintenance.cache_sync & MAINTENANCE_PENDING);
 }
 
+void plat_cleanInvalidateCache(void) {
+    if (!config_set(CONFIG_DEBUG_DISABLE_L2_CACHE)) {
+        l2cc->maintenance.clean_way = 0xffff;
+        while (l2cc->maintenance.clean_way);
+        L2_cacheSync();
+        l2cc->maintenance.inv_way = 0xffff;
+        while (l2cc->maintenance.inv_way);
+        L2_cacheSync();
+    }
+}
+
 void plat_cleanCache(void)
 {
 #ifndef CONFIG_DEBUG_DISABLE_L2_CACHE