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riscv: add remaining registers to user context.

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The registers a7, s2-11, and t3-6 were missing from seL4_UserContext.
We also add these to frameRegisters and gpRegisters, which are used
to implement the TCB invocations for reading and writing these
registers.

Zero-length arrays aren't valid expressions or types in ISO C, so
to keep the c parser happy we need to either remove gpRegisters or
provide some contents for it.

In the past, frameRegisters and gpRegisters distinguished between
those registers preserved across a syscall and those that weren't.
TCB_CopyRegisters allows the caller to choose which set to copy.

Since we preserve all non-return registers, this distinction isn't
relevant anymore and there's no easy way to justify the members of
frameRegisters and gpRegisters.

We arbitrarily choose to put the 'last' register t6 in gpRegisters,
for consistency with the register list in registerset.h and with the
order that registers are restored.
This commit is contained in:
Edward Pierzchalski 2018-12-05 12:18:02 +11:00
parent 8700b24c0d
commit 4ea62e5158
5 changed files with 37 additions and 6 deletions
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4
include/arch/riscv/arch/machine/registerset.h
View file

@ -84,8 +84,8 @@ typedef uint64_t register_t;
enum messageSizes {
n_msgRegisters = 4,
n_frameRegisters = 17,
n_gpRegisters = 0,
n_frameRegisters = 31,
n_gpRegisters = 1,
n_exceptionMessage = 3,
n_syscallMessage = 10
};

15
libsel4/arch_include/riscv/interfaces/sel4arch.xml
View file

@ -35,6 +35,21 @@
<member name="a4"/>
<member name="a5"/>
<member name="a6"/>
<member name="a7"/>
<member name="s2"/>
<member name="s3"/>
<member name="s4"/>
<member name="s5"/>
<member name="s6"/>
<member name="s7"/>
<member name="s8"/>
<member name="s9"/>
<member name="s10"/>
<member name="s11"/>
<member name="t3"/>
<member name="t4"/>
<member name="t5"/>
<member name="t6"/>
</struct>
<interface name="seL4_RISCV_PageTable" manual_name="Page Table" cap_description="Capability to the page table to invoke.">
<method id="RISCVPageTableMap" name="Map" manual_label="pagetable_map">

15
libsel4/arch_include/riscv/sel4/arch/types.h
View file

@ -55,6 +55,21 @@ typedef struct seL4_UserContext_ {
seL4_Word a4;
seL4_Word a5;
seL4_Word a6;
seL4_Word a7;
seL4_Word s2;
seL4_Word s3;
seL4_Word s4;
seL4_Word s5;
seL4_Word s6;
seL4_Word s7;
seL4_Word s8;
seL4_Word s9;
seL4_Word s10;
seL4_Word s11;
seL4_Word t3;
seL4_Word t4;
seL4_Word t5;
seL4_Word t6;
} seL4_UserContext;
typedef enum {

4
libsel4/tools/syscall_stub_gen.py
View file

@ -338,7 +338,7 @@ def init_arch_types(wordsize):
CapType("seL4_RISCV_PageTable", wordsize),
CapType("seL4_RISCV_ASIDControl", wordsize),
CapType("seL4_RISCV_ASIDPool", wordsize),
StructType("seL4_UserContext", wordsize * 17, wordsize),
StructType("seL4_UserContext", wordsize * 32, wordsize),
],
"riscv64" : [
Type("seL4_RISCV_VMAttributes", wordsize, wordsize),
@ -346,7 +346,7 @@ def init_arch_types(wordsize):
CapType("seL4_RISCV_PageTable", wordsize),
CapType("seL4_RISCV_ASIDControl", wordsize),
CapType("seL4_RISCV_ASIDPool", wordsize),
StructType("seL4_UserContext", wordsize * 17, wordsize),
StructType("seL4_UserContext", wordsize * 32, wordsize),
]
}

5
src/arch/riscv/machine/registerset.c
View file

@ -23,9 +23,10 @@ const register_t msgRegisters[] = {
};
const register_t frameRegisters[] = {
SEPC, ra, sp, gp, tp, t0, t1, t2, s0, s1, a0, a1, a2, a3, a4, a5, a6
SEPC, ra, sp, gp, tp, t0, t1, t2, s0, s1, a0, a1, a2, a3, a4, a5, a6, a7,
s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, t3, t4, t5
};
const register_t gpRegisters[] = {
t6
};