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RFC-3: Update user context for ARM with thread IDs

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Switched appropriate naming conventions.
Was using the aarch64, have switched to aarch64 names.

TIPDRURW -> tpidr_el0
TPIDRURO -> tpidrro_el0
TPIDRPRW -> tpidr_el1

Switch TLS register on aarch32 from TPIDURO (tpidrro_el0) to tpidr_ro so
that it can be written to from user-land.

Thread ID registers tpidr_el0 have been added to the user context for
aarch32 and aarch64.

Only the thread ID that is writeable from EL0 is saved in the TCB and
saved/restored on context switch.

Thread IDs that are only changed within a VM (the read-only thread ID
for exception level 0 and the thread ID for exception level 1) are
stored in the VCPU and saved and stored as part of VM enable/disable.

Thread IDs that are only changed with VMs have been separated out into
hypervisor code.
This commit is contained in:
Curtis Millar 2019-03-21 14:46:57 +11:00
parent fd83c0a3eb
commit 5646f77463
26 changed files with 181 additions and 171 deletions
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9
include/arch/arm/arch/32/mode/fastpath/fastpath.h
View file

@ -59,10 +59,6 @@ static inline void FORCE_INLINE switchToThread_fp(tcb_t *thread, pde_t *cap_pd,
benchmark_utilisation_switch(NODE_STATE(ksCurThread), thread);
#endif
#if defined(CONFIG_KERNEL_GLOBALS_FAME)
*armKSGlobalsFrame = thread->tcbIPCBuffer;
armKSGlobalsFrame[1] = getRegister(thread, TLS_BASE);
#endif
NODE_STATE(ksCurThread) = thread;
clearExMonitor_fp();
}
@ -127,11 +123,6 @@ static inline void NORETURN fastpath_restore(word_t badge, word_t msgInfo, tcb_t
restore_user_debug_context(NODE_STATE(ksCurThread));
#endif
#ifndef CONFIG_ARCH_ARM_V6
writeTPIDRURW(getRegister(NODE_STATE(ksCurThread), TPIDRURW));
writeTPIDRURO(getRegister(NODE_STATE(ksCurThread), TLS_BASE));
#endif
#ifdef CONFIG_HAVE_FPU
lazyFPURestore(NODE_STATE(ksCurThread));
#endif /* CONFIG_HAVE_FPU */

31
include/arch/arm/arch/32/mode/machine.h
View file

@ -184,20 +184,22 @@ static inline void writeTTBCR(word_t val)
static inline void writeTPIDRURW(word_t reg)
{
#ifdef CONFIG_KERNEL_GLOBALS_FRAME
armKSGlobalsFrame[GLOBALS_TPIDRURW] = reg;
#else
asm volatile("mcr p15, 0, %0, c13, c0, 2" :: "r"(reg));
#endif
}
static inline word_t readTPIDRURW(void)
{
#ifdef CONFIG_KERNEL_GLOBALS_FRAME
return armKSGlobalsFrame[GLOBALS_TPIDRURW];
#else
word_t reg;
asm volatile("mrc p15, 0, %0, c13, c0, 2" : "=r"(reg));
return reg;
}
static inline void writeTPIDRURO(word_t reg)
{
asm volatile("mcr p15, 0, %0, c13, c0, 3" :: "r"(reg));
#endif
}
static inline void writeTPIDRPRW(word_t reg)
@ -212,13 +214,18 @@ static inline word_t readTPIDRPRW(void)
return reg;
}
static inline word_t readTPIDRURO(void)
static void arm_save_thread_id(tcb_t *thread)
{
word_t reg;
asm volatile("mrc p15, 0, %0, c13, c0, 3" : "=r"(reg));
return reg;
#ifndef CONFIG_KERNEL_GLOBALS_FRAME
/* TPIDRURW is writeable from EL0 but not with globals frame. */
setRegister(thread, TPIDRURW, readTPIDRURW());
#endif /* CONFIG_KERNEL_GLOBALS_FRAME */
}
static void arm_load_thread_id(tcb_t *thread)
{
writeTPIDRURW(getRegister(thread, TPIDRURW));
}
static inline word_t readMPIDR(void)
{
@ -259,7 +266,7 @@ static inline void setKernelStack(word_t stack_address)
* Load the (per-core) kernel stack pointer to TPIDRPRW for faster reloads on traps.
*/
if (config_set(CONFIG_ARM_HYPERVISOR_SUPPORT)) {
setHTPIDR(stack_address);
writeHTPIDR(stack_address);
} else {
writeTPIDRPRW(stack_address);
}
@ -270,7 +277,7 @@ static inline word_t getKernelStack(void)
{
#ifndef CONFIG_ARCH_ARM_V6
if (config_set(CONFIG_ARM_HYPERVISOR_SUPPORT)) {
return getHTPIDR();
return readHTPIDR();
} else {
return readTPIDRPRW();
}

19
include/arch/arm/arch/32/mode/machine/registerset.h
View file

@ -42,10 +42,17 @@
#define PT_SP (13 * 4)
#define PT_NextIP (15 * 4)
#define PT_ELR_hyp (15 * 4)
#define PT_TPIDRURW (18 * 4)
#define PT_FaultIP (17 * 4)
#define PT_TPIDRURW (18 * 4)
#define PT_R8 (8 * 4)
#ifdef CONFIG_KERNEL_GLOBALS_FRAME
/*
* Virtualise the TPIDRURW register in the globals frame.
*/
#define GLOBALS_TPIDRURW 0
#endif
#ifndef __ASSEMBLER__ /* C only definitions */
#include <config.h>
@ -95,15 +102,11 @@ enum _register {
CPSR = 16,
FaultIP = 17,
TLS_BASE = 18,
#ifndef CONFIG_ARCH_ARM_V6
/* user readable/writable thread ID register.
* name comes from the ARM manual */
TPIDRURW = 19,
n_contextRegisters = 20,
#else
TPIDRURW = 18,
TLS_BASE = TPIDRURW,
n_contextRegisters = 19,
#endif
};
#define NEXT_PC_REG NextIP
@ -121,7 +124,7 @@ typedef word_t register_t;
enum messageSizes {
n_msgRegisters = seL4_FastMessageRegisters,
n_frameRegisters = 10,
n_gpRegisters = 7,
n_gpRegisters = 8,
n_exceptionMessage = 3,
n_syscallMessage = 12,
};

28
include/arch/arm/arch/32/mode/machine_pl2.h
View file

@ -173,16 +173,28 @@ static inline void setSCTLR(word_t sctlr)
asm volatile("mcr p15, 0, %0, c1, c0, 0" :: "r"(sctlr));
}
static inline void setHTPIDR(word_t htpidr)
static inline void writeTPIDRURO(word_t reg)
{
asm volatile("mcr p15, 4, %0, c13, c0, 2" :: "r"(htpidr));
asm volatile("mcr p15, 0, %0, c13, c0, 3" :: "r"(reg));
}
static inline word_t getHTPIDR(void)
static inline word_t readTPIDRURO(void)
{
word_t HTPIDR;
asm volatile("mrc p15, 4, %0, c13, c0, 2" : "=r"(HTPIDR));
return HTPIDR;
word_t reg;
asm volatile("mrc p15, 0, %0, c13, c0, 3" : "=r"(reg));
return reg;
}
static inline void writeHTPIDR(word_t reg)
{
asm volatile("mcr p15, 4, %0, c13, c0, 2" :: "r"(reg));
}
static inline word_t readHTPIDR(void)
{
word_t reg;
asm volatile("mrc p15, 4, %0, c13, c0, 2" : "=r"(reg));
return reg;
}
#else
@ -192,8 +204,8 @@ static inline void setCurrentPDPL2(paddr_t pa) {}
static inline void invalidateHypTLB(void) {}
static inline void writeContextIDPL2(word_t pd_val) {}
static inline void writeContextIDAndPD(word_t id, word_t pd_val) {}
static inline void setHTPIDR(word_t htpidr) {}
static inline word_t getHTPIDR(void)
static inline void writeHTPIDR(word_t htpidr) {}
static inline word_t readHTPIDR(void)
{
return 0;
}

11
include/arch/arm/arch/64/mode/fastpath/fastpath.h
View file

@ -40,14 +40,9 @@ switchToThread_fp(tcb_t *thread, vspace_root_t *vroot, pde_t stored_hw_asid)
asid_t asid = (asid_t)(stored_hw_asid.words[0] & 0xffff);
armv_contextSwitch(vroot, asid);
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
vcpu_switch(thread->tcbArch.tcbVCPU);
if (thread->tcbArch.tcbVCPU == NULL) {
writeTPIDRURO(thread->tcbIPCBuffer);
if (config_set(CONFIG_ARM_HYPERVISOR_SUPPORT)) {
vcpu_switch(thread->tcbArch.tcbVCPU);
}
#else
writeTPIDRURO(thread->tcbIPCBuffer);
#endif
#ifdef CONFIG_BENCHMARK_TRACK_UTILISATION
benchmark_utilisation_switch(NODE_STATE(ksCurThread), thread);
@ -115,8 +110,6 @@ static inline void NORETURN fastpath_restore(word_t badge, word_t msgInfo, tcb_t
lazyFPURestore(NODE_STATE(ksCurThread));
#endif /* CONFIG_HAVE_FPU */
writeTPIDRURW(getRegister(NODE_STATE(ksCurThread), TPIDRURW));
register word_t badge_reg asm("x0") = badge;
register word_t msgInfo_reg asm("x1") = msgInfo;
register word_t cur_thread_reg asm("x2") = (word_t)cur_thread->tcbArch.tcbContext.registers;

53
include/arch/arm/arch/64/mode/machine.h
View file

@ -68,39 +68,40 @@ static inline void writeAuxiliaryControlRegister(word_t acr)
MSR("actlr_el1", acr);
}
static inline void writeTPIDRPRW(word_t reg)
{
if (config_set(CONFIG_ARM_HYPERVISOR_SUPPORT)) {
MSR("tpidr_el2", reg);
} else {
MSR("tpidr_el1", reg);
}
}
static inline void writeTPIDRURW(word_t reg)
static inline void writeTPIDR_EL0(word_t reg)
{
MSR("tpidr_el0", reg);
}
static inline word_t readTPIDRURO(void)
{
word_t reg;
MRS("tpidrro_el0", reg);
return reg;
}
static inline void writeTPIDRURO(word_t reg)
{
MSR("tpidrro_el0", reg);
}
static inline word_t readTPIDRURW(void)
static inline word_t readTPIDR_EL0(void)
{
word_t reg;
MRS("tpidr_el0", reg);
return reg;
}
static inline void writeTPIDR_EL1(word_t reg)
{
MSR("tpidr_el1", reg);
}
static inline word_t readTPIDR_EL1(void)
{
word_t reg;
MRS("tpidr_el1", reg);
return reg;
}
static void arm_save_thread_id(tcb_t *thread)
{
setRegister(thread, TPIDR_EL0, readTPIDR_EL0());
}
static void arm_load_thread_id(tcb_t *thread)
{
writeTPIDR_EL0(getRegister(thread, TPIDR_EL0));
}
#define TCR_EL2_RES1 (BIT(23) | BIT(31))
#define TCR_EL2_T0SZ (16)
#define TCR_EL2_IRGN0_WBWC BIT(8)
@ -158,7 +159,11 @@ static inline word_t getVTTBR(void)
static inline void setKernelStack(word_t stack_address)
{
writeTPIDRPRW(stack_address);
if (config_set(CONFIG_ARM_HYPERVISOR_SUPPORT)) {
writeTPIDR_EL2(stack_address);
} else {
writeTPIDR_EL1(stack_address);
}
}
static inline void setVtable(pptr_t addr)

8
include/arch/arm/arch/64/mode/machine/registerset.h
View file

@ -78,8 +78,8 @@
#define PT_SP_EL0 (31 * 8)
#define PT_ELR_EL1 (32 * 8)
#define PT_SPSR_EL1 (33 * 8)
#define PT_TPIDRURW (35 * 8)
#define PT_FaultIP (34 * 8)
#define PT_TPIDR_EL0 (35 * 8)
#ifndef __ASSEMBLER__ /* C only definitions */
@ -142,8 +142,8 @@ enum _register {
FaultIP = 34, /* 0x110 */
/* user readable/writable thread ID register.
* name comes from the ARM manual */
TPIDRURW = 35,
TLS_BASE = 35,
TPIDR_EL0 = 35,
TLS_BASE = TPIDR_EL0,
n_contextRegisters = 36,
};
@ -158,7 +158,7 @@ typedef word_t register_t;
enum messageSizes {
n_msgRegisters = seL4_FastMessageRegisters,
n_frameRegisters = 17,
n_gpRegisters = 17,
n_gpRegisters = 18,
n_exceptionMessage = 3,
n_syscallMessage = 12,
};

36
include/arch/arm/arch/64/mode/machine_pl2.h
View file

@ -13,6 +13,42 @@
#ifndef __ARCH_MODE_MACHINE_PL2_H
#define __ARCH_MODE_MACHINE_PL2_H
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
static inline void writeTPIDRRO_EL0(word_t reg)
{
MSR("tpidrro_el0", reg);
}
static inline word_t readTPIDRRO_EL0(void)
{
word_t reg;
MRS("tpidrro_el0", reg);
return reg;
}
static inline void writeTPIDR_EL2(word_t reg)
{
MSR("tpidr_el2", reg);
}
static inline word_t readTPIDR_EL2(void)
{
word_t reg;
MRS("tpidr_el2", reg);
return reg;
}
#else
static inline void writeTPIDR_EL2(word_t reg) {}
static inline word_t readTPIDR_EL2(void)
{
return 0;
}
#endif /* End of CONFIG_ARM_HYPERVISOR_SUPPORT */
/* used in other files without guards */
static inline void setCurrentPDPL2(paddr_t pa) {}
static inline void invalidateHypTLB(void) {}

30
include/arch/arm/arch/kernel/traps.h
View file

@ -12,41 +12,17 @@
#define __KERNEL_ARM_TRAPS_H
#include <config.h>
#include <machine.h>
#include <util.h>
static inline void arch_c_entry_hook(void)
{
#ifndef CONFIG_ARCH_ARM_V6
/* If using the TPIDRURW register for the IPC buffer then
* there's no pointer in saving whatever the user put into
* it since we will overwrite it anyway next time we
* load the thread */
if (!config_set(CONFIG_IPC_BUF_TPIDRURW)) {
setRegister(NODE_STATE(ksCurThread), TPIDRURW, readTPIDRURW());
}
#endif
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
if (NODE_STATE(ksCurThread)->tcbArch.tcbVCPU) {
/* Although the TPIDRURO register is user read only it *is* writeable
* by a thread running in supervisor mode and so in that case we need to
* save it here as it actually could have changed */
#ifndef CONFIG_ARCH_AARCH64
setRegister(NODE_STATE(ksCurThread), TLS_BASE, readTPIDRURO());
#endif
/* in the case where we are using TPIDRURW as the IPC buffer we still
* want to save the value of TPIDRURW (even though we skipped it just
* above) as a supervisor mode thread will not understand or appreciate
* seL4s desire that it be used as the IPC buffer and so we should respect
* its changes */
if (config_set(CONFIG_IPC_BUF_TPIDRURW)) {
setRegister(NODE_STATE(ksCurThread), TPIDRURW, readTPIDRURW());
}
}
#endif
arm_save_thread_id(NODE_STATE(ksCurThread));
}
static inline void arch_c_exit_hook(void)
{
arm_load_thread_id(NODE_STATE(ksCurThread));
}
void VISIBLE NORETURN restore_user_context(void);

4
include/arch/arm/arch/model/statedata.h
View file

@ -34,4 +34,8 @@ NODE_STATE_END(archNodeState);
extern user_breakpoint_state_t armKSNullBreakpointState VISIBLE;
#endif
#ifdef CONFIG_KERNEL_GLOBALS_FRAME
extern word_t armKSGlobalsFrame[BIT(ARMSmallPageBits) / sizeof(word_t)];
#endif
#endif /* __ARCH_MODEL_STATEDATA_H */

5
include/arch/arm/armv/armv7-a/armv/vcpu.h
View file

@ -333,6 +333,8 @@ static word_t vcpu_hw_read_reg(word_t reg_index)
return getCIDR();
case seL4_VCPUReg_TPIDRPRW:
return readTPIDRPRW();
case seL4_VCPUReg_TPIDRURO:
return readTPIDRURO();
case seL4_VCPUReg_FPEXC:
return reg;
case seL4_VCPUReg_CNTV_TVAL:
@ -435,6 +437,9 @@ static void vcpu_hw_write_reg(word_t reg_index, word_t reg)
case seL4_VCPUReg_TPIDRPRW:
writeTPIDRPRW(reg);
break;
case seL4_VCPUReg_TPIDRURO:
writeTPIDRURO(reg);
break;
case seL4_VCPUReg_FPEXC:
break;
case seL4_VCPUReg_CNTV_TVAL:

40
include/arch/arm/armv/armv8-a/64/armv/vcpu.h
View file

@ -277,42 +277,6 @@ static inline void writeVBAR(word_t reg)
MSR(REG_VBAR_EL1, reg);
}
static inline word_t readTPIDR_EL0(void)
{
word_t reg;
MRS(REG_TPIDR_EL0, reg);
return reg;
}
static inline void writeTPIDR_EL0(word_t reg)
{
MSR(REG_TPIDR_EL0, reg);
}
static inline word_t readTPIDR_EL1(void)
{
word_t reg;
MRS(REG_TPIDR_EL1, reg);
return reg;
}
static inline void writeTPIDR_EL1(word_t reg)
{
MSR(REG_TPIDR_EL1, reg);
}
static inline word_t readTPIDRRO_EL0(void)
{
word_t reg;
MRS(REG_TPIDRRO_EL0, reg);
return reg;
}
static inline void writeTPIDRRO_EL0(word_t reg)
{
MSR(REG_TPIDRRO_EL0, reg);
}
static inline word_t readSP_EL1(void)
{
word_t reg;
@ -419,8 +383,6 @@ static word_t vcpu_hw_read_reg(word_t reg_index)
return readISR();
case seL4_VCPUReg_VBAR:
return readVBAR();
case seL4_VCPUReg_TPIDR_EL0:
return readTPIDR_EL0();
case seL4_VCPUReg_TPIDR_EL1:
return readTPIDR_EL1();
case seL4_VCPUReg_TPIDRRO_EL0:
@ -478,8 +440,6 @@ static void vcpu_hw_write_reg(word_t reg_index, word_t reg)
return;
case seL4_VCPUReg_VBAR:
return writeVBAR(reg);
case seL4_VCPUReg_TPIDR_EL0:
return writeTPIDR_EL0(reg);
case seL4_VCPUReg_TPIDR_EL1:
return writeTPIDR_EL1(reg);
case seL4_VCPUReg_TPIDRRO_EL0:

1
libsel4/sel4_arch_include/aarch32/interfaces/sel4arch.xml
View file

@ -29,6 +29,7 @@
<member name="r6"/>
<member name="r7"/>
<member name="r14"/>
<member name="tpidrurw"/>
</struct>
<interface name="seL4_ARM_PageDirectory" manual_name="Page Directory">
<method id="ARMPDClean_Data" name="Clean_Data" manual_name="Clean Data" manual_label="pd_clean">

1
libsel4/sel4_arch_include/aarch32/sel4/sel4_arch/constants.h
View file

@ -96,6 +96,7 @@ enum {
seL4_VCPUReg_NMRR,
seL4_VCPUReg_CIDR,
seL4_VCPUReg_TPIDRPRW,
seL4_VCPUReg_TPIDRURO,
seL4_VCPUReg_FPEXC,
seL4_VCPUReg_CNTV_TVAL,
seL4_VCPUReg_CNTV_CTL,

2
libsel4/sel4_arch_include/aarch32/sel4/sel4_arch/types.h
View file

@ -26,6 +26,8 @@ typedef struct seL4_UserContext_ {
seL4_Word pc, sp, cpsr, r0, r1, r8, r9, r10, r11, r12;
/* other integer registers */
seL4_Word r2, r3, r4, r5, r6, r7, r14;
/* Thread ID registers */
seL4_Word tpidrurw;
} seL4_UserContext;
#endif /* __LIBSEL4_SEL4_ARCH_TYPES_H */

1
libsel4/sel4_arch_include/aarch64/interfaces/sel4arch.xml
View file

@ -46,6 +46,7 @@
<member name="x26"/>
<member name="x27"/>
<member name="x28"/>
<member name="tpidr_el0"/>
</struct>
<interface name="seL4_ARM_PageGlobalDirectory" manual_name="Page Global Directory">
<method id="ARMPageGlobalDirectoryClean_Data" name="Clean_Data" manual_label="pgd_clean"

1
libsel4/sel4_arch_include/aarch64/sel4/sel4_arch/constants.h
View file

@ -97,7 +97,6 @@ enum {
seL4_VCPUReg_VBAR,
/* thread pointer/ID registers EL0/EL1 */
seL4_VCPUReg_TPIDR_EL0,
seL4_VCPUReg_TPIDR_EL1,
seL4_VCPUReg_TPIDRRO_EL0,

2
libsel4/sel4_arch_include/aarch64/sel4/sel4_arch/types.h
View file

@ -29,6 +29,8 @@ typedef struct seL4_UserContext_ {
seL4_Word pc, sp, spsr, x0, x1, x2, x3, x4, x5, x6, x7, x8, x16, x17, x18, x29, x30;
/* other integer registers */
seL4_Word x9, x10, x11, x12, x13, x14, x15, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28;
/* Thread ID registers */
seL4_Word tpidr_el0;
} seL4_UserContext;
#endif /* __LIBSEL4_SEL4_SEL4_ARCH_TYPES_H_ */

6
libsel4/tools/syscall_stub_gen.py
View file

@ -273,7 +273,7 @@ def init_arch_types(wordsize):
CapType("seL4_ARM_VCPU", wordsize),
CapType("seL4_ARM_IOSpace", wordsize),
CapType("seL4_ARM_IOPageTable", wordsize),
StructType("seL4_UserContext", wordsize * 17, wordsize),
StructType("seL4_UserContext", wordsize * 18, wordsize),
],
"aarch64": [
@ -288,7 +288,7 @@ def init_arch_types(wordsize):
CapType("seL4_ARM_VCPU", wordsize),
CapType("seL4_ARM_IOSpace", wordsize),
CapType("seL4_ARM_IOPageTable", wordsize),
StructType("seL4_UserContext", wordsize * 34, wordsize),
StructType("seL4_UserContext", wordsize * 35, wordsize),
],
"arm_hyp": [
@ -301,7 +301,7 @@ def init_arch_types(wordsize):
CapType("seL4_ARM_VCPU", wordsize),
CapType("seL4_ARM_IOSpace", wordsize),
CapType("seL4_ARM_IOPageTable", wordsize),
StructType("seL4_UserContext", wordsize * 17, wordsize),
StructType("seL4_UserContext", wordsize * 18, wordsize),
],
"ia32": [

5
src/arch/arm/32/c_traps.c
View file

@ -38,11 +38,6 @@ void VISIBLE NORETURN restore_user_context(void)
lazyFPURestore(NODE_STATE(ksCurThread));
#endif /* CONFIG_HAVE_FPU */
#ifndef CONFIG_ARCH_ARM_V6
writeTPIDRURW(getRegister(NODE_STATE(ksCurThread), TPIDRURW));
writeTPIDRURO(getRegister(NODE_STATE(ksCurThread), TLS_BASE));
#endif
if (config_set(CONFIG_ARM_HYPERVISOR_SUPPORT)) {
asm volatile(
/* Set stack pointer to point at the r0 of the user context. */

9
src/arch/arm/32/kernel/thread.c
View file

@ -19,10 +19,6 @@
void Arch_switchToThread(tcb_t *tcb)
{
setVMRoot(tcb);
#if defined(CONFIG_KERNEL_GLOBALS_FAME)
*armKSGlobalsFrame = tcb->tcbIPCBuffer;
armKSGlobalsFrame[1] = getRegister(tcb, TLS_BASE);
#endif
clearExMonitor();
}
@ -40,11 +36,6 @@ void Arch_switchToIdleThread(void)
/* Force the idle thread to run on kernel page table */
setVMRoot(NODE_STATE(ksIdleThread));
#ifdef CONFIG_KERNEL_GLOBALS_FAME
*armKSGlobalsFrame = 0;
armKSGlobalsFrame[1] = 0;
#endif /* CONFIG_KERNEL_GLOBALS_FAME */
}
void Arch_activateIdleThread(tcb_t *tcb)

16
src/arch/arm/32/machine/registerset.c
View file

@ -8,18 +8,32 @@
* @TAG(GD_GPL)
*/
#include <assert.h>
#include <arch/machine/registerset.h>
const register_t msgRegisters[] = {
R2, R3, R4, R5
};
compile_assert(
consistent_message_registers,
sizeof(msgRegisters) / sizeof(msgRegisters[0]) == n_msgRegisters
);
const register_t frameRegisters[] = {
FaultIP, SP, CPSR,
R0, R1, R8, R9, R10, R11, R12
};
compile_assert(
consistent_frame_registers,
sizeof(frameRegisters) / sizeof(frameRegisters[0]) == n_frameRegisters
);
const register_t gpRegisters[] = {
R2, R3, R4, R5, R6, R7, R14
R2, R3, R4, R5, R6, R7, R14,
TPIDRURW,
};
compile_assert(
consistent_gp_registers,
sizeof(gpRegisters) / sizeof(gpRegisters[0]) == n_gpRegisters
);

2
src/arch/arm/64/c_traps.c
View file

@ -32,8 +32,6 @@ void VISIBLE NORETURN restore_user_context(void)
lazyFPURestore(NODE_STATE(ksCurThread));
#endif /* CONFIG_HAVE_FPU */
writeTPIDRURW(getRegister(NODE_STATE(ksCurThread), TPIDRURW));
asm volatile(
"mov sp, %0 \n"

8
src/arch/arm/64/kernel/thread.c
View file

@ -20,13 +20,6 @@
void Arch_switchToThread(tcb_t *tcb)
{
setVMRoot(tcb);
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
/* Do not overwrite the TPIDRRO_EL0 for a VCPU */
if (tcb->tcbArch.tcbVCPU) {
return;
}
#endif
writeTPIDRURO(tcb->tcbIPCBuffer);
}
BOOT_CODE void Arch_configureIdleThread(tcb_t *tcb)
@ -41,7 +34,6 @@ void Arch_switchToIdleThread(void)
vcpu_switch(NULL);
}
setCurrentUserVSpaceRoot(ttbr_new(0, pptr_to_paddr(armKSGlobalUserPGD)));
writeTPIDRURO(0);
}
void Arch_activateIdleThread(tcb_t *tcb)

16
src/arch/arm/64/machine/registerset.c
View file

@ -10,18 +10,32 @@
* @TAG(DATA61_GPL)
*/
#include <assert.h>
#include <arch/machine/registerset.h>
const register_t msgRegisters[] = {
X2, X3, X4, X5
};
compile_assert(
consistent_message_registers,
sizeof(msgRegisters) / sizeof(msgRegisters[0]) == n_msgRegisters
);
const register_t frameRegisters[] = {
FaultIP, SP_EL0, SPSR_EL1,
X0, X1, X2, X3, X4, X5, X6, X7, X8, X16, X17, X18, X29, X30
};
compile_assert(
consistent_frame_registers,
sizeof(frameRegisters) / sizeof(frameRegisters[0]) == n_frameRegisters
);
const register_t gpRegisters[] = {
X9, X10, X11, X12, X13, X14, X15,
X19, X20, X21, X22, X23, X24, X25, X26, X27, X28
X19, X20, X21, X22, X23, X24, X25, X26, X27, X28,
TPIDR_EL0,
};
compile_assert(
consistent_gp_registers,
sizeof(gpRegisters) / sizeof(gpRegisters[0]) == n_gpRegisters
);

8
src/arch/arm/object/vcpu.c
View file

@ -96,9 +96,11 @@ static inline void access_fpexc(vcpu_t *vcpu, bool_t write)
static void vcpu_enable(vcpu_t *vcpu)
{
#ifdef CONFIG_ARCH_AARCH64
vcpu_restore_reg(vcpu, seL4_VCPUReg_TPIDRRO_EL0);
armv_vcpu_enable(vcpu);
#else
vcpu_restore_reg(vcpu, seL4_VCPUReg_SCTLR);
vcpu_restore_reg(vcpu, seL4_VCPUReg_TPIDRURO);
setHCR(HCR_VCPU);
isb();
@ -175,11 +177,17 @@ static void vcpu_enable(vcpu_t *vcpu)
static void vcpu_disable(vcpu_t *vcpu)
{
#ifdef CONFIG_ARCH_AARCH64
if (likely(vcpu)) {
vcpu_save_reg(vcpu, seL4_VCPUReg_TPIDRRO_EL0);
vcpu_hw_write_reg(seL4_VCPUReg_TPIDRRO_EL0, 0);
}
armv_vcpu_disable(vcpu);
#else
uint32_t hcr;
dsb();
if (likely(vcpu)) {
vcpu_save_reg(vcpu, seL4_VCPUReg_TPIDRURO);
vcpu_hw_write_reg(seL4_VCPUReg_TPIDRURO, 0);
hcr = get_gic_vcpu_ctrl_hcr();
vcpu->vgic.hcr = hcr;
vcpu_save_reg(vcpu, seL4_VCPUReg_SCTLR);