From 58f0e87355225a3d3fddbfdf62b298b083493d1c Mon Sep 17 00:00:00 2001 From: Ivan-Velickovic Date: Tue, 11 Feb 2025 14:08:41 +1100 Subject: [PATCH] Add support for SiFive Premier P550 platform The SiFive Premier P550 [1] is a new development board from SiFive that is based on the ESWIN EIC7700X SoC. The platform is interesting to the seL4 community as it implements the RISC-V hypervisor extension meaning we now have real hardware to evaluate RISC-V hypervisor changes to seL4. It also implements the Sscofpmf extension and so we'll be able to get more experiment with proper profiling on RISC-V. Unfortunately, it seems we still do not have proper ASID suppor according to [2]. The board comes in two configurations, 16GB and 32GB of memory. This adds support for the 16GB model. The DTS comes from SiFive's fork of Linux [3]. No modifications were made, any extra things are in the overlay. [1]: https://www.sifive.com/boards/hifive-premier-p550 [2]: https://forums.sifive.com/t/asid-vmid-support-in-p550-eic7700x/6887 [3]: https://github.com/sifive/riscv-linux/tree/dev/kernel/hifive-premier-p550 Signed-off-by: Ivan-Velickovic --- include/drivers/irq/riscv_plic0.h | 3 +- .../hifive-p550/sel4/plat/api/constants.h | 9 + src/plat/eswin/config.cmake | 30 + src/plat/eswin/overlay-hifive-p550.dts | 49 + tools/dts/hifive-p550.dts | 5362 +++++++++++++++++ 5 files changed, 5452 insertions(+), 1 deletion(-) create mode 100644 libsel4/sel4_plat_include/hifive-p550/sel4/plat/api/constants.h create mode 100644 src/plat/eswin/config.cmake create mode 100644 src/plat/eswin/overlay-hifive-p550.dts create mode 100644 tools/dts/hifive-p550.dts diff --git a/include/drivers/irq/riscv_plic0.h b/include/drivers/irq/riscv_plic0.h index 55ff740ba..a2b558c11 100644 --- a/include/drivers/irq/riscv_plic0.h +++ b/include/drivers/irq/riscv_plic0.h @@ -18,7 +18,8 @@ !defined(CONFIG_PLAT_ROCKETCHIP_ZCU102) && \ !defined(CONFIG_PLAT_STAR64) && \ !defined(CONFIG_PLAT_CHESHIRE) && \ - !defined(CONFIG_PLAT_ARIANE) + !defined(CONFIG_PLAT_ARIANE) && \ + !defined(CONFIG_PLAT_HIFIVE_P550) #error "Check if this platform supports a PLIC." #endif diff --git a/libsel4/sel4_plat_include/hifive-p550/sel4/plat/api/constants.h b/libsel4/sel4_plat_include/hifive-p550/sel4/plat/api/constants.h new file mode 100644 index 000000000..ba4dad9c4 --- /dev/null +++ b/libsel4/sel4_plat_include/hifive-p550/sel4/plat/api/constants.h @@ -0,0 +1,9 @@ +/* + * Copyright 2025, UNSW + * + * SPDX-License-Identifier: BSD-2-Clause + */ + +#pragma once + +#include diff --git a/src/plat/eswin/config.cmake b/src/plat/eswin/config.cmake new file mode 100644 index 000000000..4da3ffb9f --- /dev/null +++ b/src/plat/eswin/config.cmake @@ -0,0 +1,30 @@ +# +# Copyright 2025, UNSW +# +# SPDX-License-Identifier: GPL-2.0-only +# + +cmake_minimum_required(VERSION 3.7.2) + +declare_platform(hifive-p550 KernelPlatformHifiveP550 PLAT_HIFIVE_P550 KernelArchRiscV) + +if(KernelPlatformHifiveP550) + declare_seL4_arch(riscv64) + config_set(KernelRiscVPlatform RISCV_PLAT ${KernelPlatform}) + config_set(KernelPlatformFirstHartID FIRST_HART_ID 0) + config_set(KernelOpenSBIPlatform OPENSBI_PLATFORM "generic") + # Note that by default the kernel is configured for the 16GB model. + list(APPEND KernelDTSList "tools/dts/${KernelPlatform}.dts") + list(APPEND KernelDTSList "${CMAKE_CURRENT_LIST_DIR}/overlay-${KernelPlatform}.dts") + # The value for TIMER_FREQUENCY is from the "timebase-frequency" field on + # the "cpus" node in the HiFive P550 device tree. + # The value for MAX_IRQ comes from the DTS "interrupt-controller" node which says + # "riscv,ndev = <0x208>". + declare_default_headers( + TIMER_FREQUENCY 1000000 + MAX_IRQ 520 + INTERRUPT_CONTROLLER drivers/irq/riscv_plic0.h + ) +else() + unset(KernelPlatformFirstHartID CACHE) +endif() diff --git a/src/plat/eswin/overlay-hifive-p550.dts b/src/plat/eswin/overlay-hifive-p550.dts new file mode 100644 index 000000000..238158804 --- /dev/null +++ b/src/plat/eswin/overlay-hifive-p550.dts @@ -0,0 +1,49 @@ +/* + * Copyright 2025, UNSW + * + * SPDX-License-Identifier: GPL-2.0-only + */ + +/ { + reserved-memory { + /delete-node/ linux,cma; + }; + + chosen { + seL4,kernel-devices = + &{/soc/clint@2000000}, + &{/soc/interrupt-controller@c000000}; + }; + + /* 16GiB of main memory */ + memory@80000000 { + reg = <0x00 0x80000000 0x04 0x00>; + }; + + /* + * According to the EIC7700X SoC manual the CLINT is mapped from + * 0x0200_0000 to 0x0200_C000. + */ + soc { + clint@2000000 { + compatible = "riscv,cpu-intc"; + reg = <0x00000000 0x2000000 0x00000000 0x00000c000>; + }; + }; + + /* Reserve 2 MiB for SBI at the start of RAM (0x40000000 - 0x40200000). This + * is exactly one "megapage" in the MMU table. It leaves plenty of space for + * further SBI experimenting, given the known usage (as of June 2021) is: + * - BBL: 76 KiB (= 0x13000) + * - OpenSBI: 128 KiB (= 0x20000) with PMP protection + */ + reserved-memory { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + sbi@40000000 { + reg = <0x0 0x80000000 0x0 0x200000>; + no-map; + }; + }; +}; diff --git a/tools/dts/hifive-p550.dts b/tools/dts/hifive-p550.dts new file mode 100644 index 000000000..81bc8e193 --- /dev/null +++ b/tools/dts/hifive-p550.dts @@ -0,0 +1,5362 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved. +/dts-v1/; + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "sifive,hifive-premier-p550", "eswin,eic7700"; + model = "SiFive HiFive Premier P550"; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + timebase-frequency = <0xf4240>; + + cpu@0 { + clock-frequency = <0x00>; + compatible = "eswin,eic770x", "riscv"; + d-cache-block-size = <0x40>; + d-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-tlb-sets = <0x01>; + d-tlb-size = <0x20>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0x04>; + hwpf-distanceBits = <0x06>; + hwpf-hitCacheThrdBits = <0x05>; + hwpf-hitMSHRThrdBits = <0x04>; + hwpf-l2pfPoolSize = <0x0a>; + hwpf-nIssQEnt = <0x06>; + hwpf-nPrefetchQueueEntries = <0x08>; + hwpf-nStreams = <0x10>; + hwpf-qFullnessThrdBits = <0x04>; + hwpf-windowBits = <0x06>; + i-cache-block-size = <0x40>; + i-cache-sets = <0x80>; + i-cache-size = <0x8000>; + i-tlb-sets = <0x01>; + i-tlb-size = <0x20>; + mmu-type = "riscv,sv48"; + next-level-cache = <0x01>; + reg = <0x00>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicsr", "zifencei", "zba", "zbb", "sscofpmf"; + riscv,pmpgranularity = <0x1000>; + riscv,pmpregions = <0x08>; + sifive,buserror = <0x02>; + status = "okay"; + timebase-frequency = <0xf4240>; + tlb-split; + clocks = <0x03 0x1f4>; + operating-points-v2 = <0x04>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x05>; + }; + + pmu { + riscv,raw-event-to-mhpmcounters = <0x00 0x00 0xffffffff 0xff 0x78 0x00 0x01 0xffffffff 0xfffe07ff 0x78 0x00 0x02 0xffffffff 0xfffe00ff 0x78 0x00 0x03 0xfffffffc 0xff 0x78 0x00 0x04 0xffffffc0 0xff 0x78 0x00 0x05 0xffffffff 0xfffffdff 0x78 0x00 0x06 0xfffffe00 0x110204ff 0x78 0x00 0x07 0xffffffff 0xf00000ff 0x78 0x00 0x08 0xfffffe04 0xff 0x78 0x00 0x09 0xffffffff 0xffffc0ff 0x78 0x00 0x0a 0xffffffff 0xf00000ff 0x78 0x00 0x0b 0xffffffff 0xfffffcff 0x78 0x00 0x0c 0xfffffff0 0xff 0x78 0x00 0x0d 0xffffffff 0x800000ff 0x78 0x00 0x0e 0xffffffff 0xf80000ff 0x78 0x00 0x0f 0xfffffffc 0xff 0x78>; + riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x04 0x06 0x78 0x10009 0x10009 0x78 0x10019 0x10019 0x78 0x10021 0x10021 0x78>; + riscv,event-to-mhpmevent = <0x04 0x00 0x202 0x05 0x00 0x4000 0x06 0x00 0x2001 0x10009 0x00 0x102 0x10019 0x00 0x1002 0x10021 0x00 0x802>; + compatible = "riscv,pmu0", "riscv,pmu"; + interrupts-extended = <0x05 0x0d>; + }; + }; + + cpu@1 { + clock-frequency = <0x00>; + compatible = "eswin,eic770x", "riscv"; + d-cache-block-size = <0x40>; + d-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-tlb-sets = <0x01>; + d-tlb-size = <0x20>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0x04>; + hwpf-distanceBits = <0x06>; + hwpf-hitCacheThrdBits = <0x05>; + hwpf-hitMSHRThrdBits = <0x04>; + hwpf-l2pfPoolSize = <0x0a>; + hwpf-nIssQEnt = <0x06>; + hwpf-nPrefetchQueueEntries = <0x08>; + hwpf-nStreams = <0x10>; + hwpf-qFullnessThrdBits = <0x04>; + hwpf-windowBits = <0x06>; + i-cache-block-size = <0x40>; + i-cache-sets = <0x80>; + i-cache-size = <0x8000>; + i-tlb-sets = <0x01>; + i-tlb-size = <0x20>; + mmu-type = "riscv,sv48"; + next-level-cache = <0x06>; + reg = <0x01>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicsr", "zifencei", "zba", "zbb", "sscofpmf"; + riscv,pmpgranularity = <0x1000>; + riscv,pmpregions = <0x08>; + sifive,buserror = <0x07>; + status = "okay"; + timebase-frequency = <0xf4240>; + tlb-split; + clocks = <0x03 0x1f5>; + operating-points-v2 = <0x04>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x08>; + }; + + pmu { + riscv,raw-event-to-mhpmcounters = <0x00 0x00 0xffffffff 0xff 0x78 0x00 0x01 0xffffffff 0xfffe07ff 0x78 0x00 0x02 0xffffffff 0xfffe00ff 0x78 0x00 0x03 0xfffffffc 0xff 0x78 0x00 0x04 0xffffffc0 0xff 0x78 0x00 0x05 0xffffffff 0xfffffdff 0x78 0x00 0x06 0xfffffe00 0x110204ff 0x78 0x00 0x07 0xffffffff 0xf00000ff 0x78 0x00 0x08 0xfffffe04 0xff 0x78 0x00 0x09 0xffffffff 0xffffc0ff 0x78 0x00 0x0a 0xffffffff 0xf00000ff 0x78 0x00 0x0b 0xffffffff 0xfffffcff 0x78 0x00 0x0c 0xfffffff0 0xff 0x78 0x00 0x0d 0xffffffff 0x800000ff 0x78 0x00 0x0e 0xffffffff 0xf80000ff 0x78 0x00 0x0f 0xfffffffc 0xff 0x78>; + riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x04 0x06 0x78 0x10009 0x10009 0x78 0x10019 0x10019 0x78 0x10021 0x10021 0x78>; + riscv,event-to-mhpmevent = <0x04 0x00 0x202 0x05 0x00 0x4000 0x06 0x00 0x2001 0x10009 0x00 0x102 0x10019 0x00 0x1002 0x10021 0x00 0x802>; + compatible = "riscv,pmu0", "riscv,pmu"; + interrupts-extended = <0x08 0x0d>; + }; + }; + + cpu@2 { + clock-frequency = <0x00>; + compatible = "eswin,eic770x", "riscv"; + d-cache-block-size = <0x40>; + d-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-tlb-sets = <0x01>; + d-tlb-size = <0x20>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0x04>; + hwpf-distanceBits = <0x06>; + hwpf-hitCacheThrdBits = <0x05>; + hwpf-hitMSHRThrdBits = <0x04>; + hwpf-l2pfPoolSize = <0x0a>; + hwpf-nIssQEnt = <0x06>; + hwpf-nPrefetchQueueEntries = <0x08>; + hwpf-nStreams = <0x10>; + hwpf-qFullnessThrdBits = <0x04>; + hwpf-windowBits = <0x06>; + i-cache-block-size = <0x40>; + i-cache-sets = <0x80>; + i-cache-size = <0x8000>; + i-tlb-sets = <0x01>; + i-tlb-size = <0x20>; + mmu-type = "riscv,sv48"; + next-level-cache = <0x09>; + reg = <0x02>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicsr", "zifencei", "zba", "zbb", "sscofpmf"; + riscv,pmpgranularity = <0x1000>; + riscv,pmpregions = <0x08>; + sifive,buserror = <0x0a>; + status = "okay"; + timebase-frequency = <0xf4240>; + tlb-split; + clocks = <0x03 0x1f6>; + operating-points-v2 = <0x04>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x0b>; + }; + + pmu { + riscv,raw-event-to-mhpmcounters = <0x00 0x00 0xffffffff 0xff 0x78 0x00 0x01 0xffffffff 0xfffe07ff 0x78 0x00 0x02 0xffffffff 0xfffe00ff 0x78 0x00 0x03 0xfffffffc 0xff 0x78 0x00 0x04 0xffffffc0 0xff 0x78 0x00 0x05 0xffffffff 0xfffffdff 0x78 0x00 0x06 0xfffffe00 0x110204ff 0x78 0x00 0x07 0xffffffff 0xf00000ff 0x78 0x00 0x08 0xfffffe04 0xff 0x78 0x00 0x09 0xffffffff 0xffffc0ff 0x78 0x00 0x0a 0xffffffff 0xf00000ff 0x78 0x00 0x0b 0xffffffff 0xfffffcff 0x78 0x00 0x0c 0xfffffff0 0xff 0x78 0x00 0x0d 0xffffffff 0x800000ff 0x78 0x00 0x0e 0xffffffff 0xf80000ff 0x78 0x00 0x0f 0xfffffffc 0xff 0x78>; + riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x04 0x06 0x78 0x10009 0x10009 0x78 0x10019 0x10019 0x78 0x10021 0x10021 0x78>; + riscv,event-to-mhpmevent = <0x04 0x00 0x202 0x05 0x00 0x4000 0x06 0x00 0x2001 0x10009 0x00 0x102 0x10019 0x00 0x1002 0x10021 0x00 0x802>; + compatible = "riscv,pmu0", "riscv,pmu"; + interrupts-extended = <0x0b 0x0d>; + }; + }; + + cpu@3 { + clock-frequency = <0x00>; + compatible = "eswin,eic770x", "riscv"; + d-cache-block-size = <0x40>; + d-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-tlb-sets = <0x01>; + d-tlb-size = <0x20>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0x04>; + hwpf-distanceBits = <0x06>; + hwpf-hitCacheThrdBits = <0x05>; + hwpf-hitMSHRThrdBits = <0x04>; + hwpf-l2pfPoolSize = <0x0a>; + hwpf-nIssQEnt = <0x06>; + hwpf-nPrefetchQueueEntries = <0x08>; + hwpf-nStreams = <0x10>; + hwpf-qFullnessThrdBits = <0x04>; + hwpf-windowBits = <0x06>; + i-cache-block-size = <0x40>; + i-cache-sets = <0x80>; + i-cache-size = <0x8000>; + i-tlb-sets = <0x01>; + i-tlb-size = <0x20>; + mmu-type = "riscv,sv48"; + next-level-cache = <0x0c>; + reg = <0x03>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicsr", "zifencei", "zba", "zbb", "sscofpmf"; + riscv,pmpgranularity = <0x1000>; + riscv,pmpregions = <0x08>; + sifive,buserror = <0x0d>; + status = "okay"; + timebase-frequency = <0xf4240>; + tlb-split; + clocks = <0x03 0x1f7>; + operating-points-v2 = <0x04>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x0e>; + }; + + pmu { + riscv,raw-event-to-mhpmcounters = <0x00 0x00 0xffffffff 0xff 0x78 0x00 0x01 0xffffffff 0xfffe07ff 0x78 0x00 0x02 0xffffffff 0xfffe00ff 0x78 0x00 0x03 0xfffffffc 0xff 0x78 0x00 0x04 0xffffffc0 0xff 0x78 0x00 0x05 0xffffffff 0xfffffdff 0x78 0x00 0x06 0xfffffe00 0x110204ff 0x78 0x00 0x07 0xffffffff 0xf00000ff 0x78 0x00 0x08 0xfffffe04 0xff 0x78 0x00 0x09 0xffffffff 0xffffc0ff 0x78 0x00 0x0a 0xffffffff 0xf00000ff 0x78 0x00 0x0b 0xffffffff 0xfffffcff 0x78 0x00 0x0c 0xfffffff0 0xff 0x78 0x00 0x0d 0xffffffff 0x800000ff 0x78 0x00 0x0e 0xffffffff 0xf80000ff 0x78 0x00 0x0f 0xfffffffc 0xff 0x78>; + riscv,event-to-mhpmcounters = <0x01 0x01 0x01 0x02 0x02 0x02 0x04 0x06 0x78 0x10009 0x10009 0x78 0x10019 0x10019 0x78 0x10021 0x10021 0x78>; + riscv,event-to-mhpmevent = <0x04 0x00 0x202 0x05 0x00 0x4000 0x06 0x00 0x2001 0x10009 0x00 0x102 0x10019 0x00 0x1002 0x10021 0x00 0x802>; + compatible = "riscv,pmu0", "riscv,pmu"; + interrupts-extended = <0x0e 0x0d>; + }; + }; + }; + + memory@80000000 { + compatible = "sifive,axi4-mem-port", "sifive,axi4-port", "sifive,mem-port"; + device_type = "memory"; + reg = <0x00 0x80000000 0x7f 0x80000000>; + sifive,port-width-bytes = <0x20>; + phandle = <0x13>; + }; + + soc { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "SiFive,FU800-soc", "fu800-soc", "sifive-soc", "simple-bus"; + ranges; + + authentication-controller { + compatible = "sifive,authentication0"; + sifive,auth-types = "fuse"; + }; + + axi4-sys-port@40000000 { + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-external-bus", "simple-bus"; + ranges = <0x40000000 0x00 0x40000000 0x40000000>; + sifive,port-width-bytes = <0x10>; + }; + + axi4-sys-port@8000000000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-external-bus", "simple-bus"; + ranges = <0x80 0x00 0x80 0x00 0x180 0x00>; + sifive,port-width-bytes = <0x10>; + }; + + basic-bus-blocker@200000 { + compatible = "sifive,basic-bus-blocker1"; + reg = <0x00 0x200000 0x00 0x1000>; + reg-names = "control"; + }; + + basic-bus-blocker@202000 { + compatible = "sifive,basic-bus-blocker1"; + reg = <0x00 0x202000 0x00 0x1000>; + reg-names = "control"; + }; + + basic-bus-blocker@204000 { + compatible = "sifive,basic-bus-blocker1"; + reg = <0x00 0x204000 0x00 0x1000>; + reg-names = "control"; + }; + + burst-bundler@10010000 { + compatible = "sifive,burst-bundler0"; + reg = <0x00 0x10010000 0x00 0x1000>; + reg-names = "control"; + }; + + bus-error-unit@hart0 { + compatible = "sifive,buserror"; + interrupt-parent = <0x0f>; + interrupts = <0x205>; + reg = <0x00 0x1700000 0x00 0x1000>; + reg-names = "control"; + phandle = <0x02>; + }; + + bus-error-unit@hart1 { + compatible = "sifive,buserror"; + interrupt-parent = <0x0f>; + interrupts = <0x206>; + reg = <0x00 0x1701000 0x00 0x1000>; + reg-names = "control"; + phandle = <0x07>; + }; + + bus-error-unit@hart2 { + compatible = "sifive,buserror"; + interrupt-parent = <0x0f>; + interrupts = <0x207>; + reg = <0x00 0x1702000 0x00 0x1000>; + reg-names = "control"; + phandle = <0x0a>; + }; + + bus-error-unit@hart3 { + compatible = "sifive,buserror"; + interrupt-parent = <0x0f>; + interrupts = <0x208>; + reg = <0x00 0x1703000 0x00 0x1000>; + reg-names = "control"; + phandle = <0x0d>; + }; + + cache-controller@2010000 { + cache-block-size = <0x40>; + cache-level = <0x03>; + cache-sets = <0x1000>; + cache-size = <0x400000>; + cache-unified; + compatible = "sifive,eic7700"; + interrupt-parent = <0x0f>; + interrupts = <0x01 0x03 0x04 0x02>; + next-level-cache = <0x10 0x11 0x12 0x13>; + reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x400000>; + reg-names = "control", "sideband"; + sifive,a-mshr-count = <0x3c>; + sifive,bank-count = <0x04>; + sifive,ecc-granularity = <0x08>; + sifive,max-master-id = <0x0d>; + sifive,perfmon-counters = <0x06>; + numa-node-id = <0x00>; + phandle = <0x14>; + }; + + debug-controller@0 { + compatible = "sifive,debug-100", "riscv,debug-100"; + debug-attach = "jtag"; + reg = <0x00 0x00 0x00 0x1000>; + reg-names = "control"; + }; + + error-device@1000 { + compatible = "sifive,error0"; + reg = <0x00 0x1000 0x00 0x3000 0x00 0x5000 0x00 0x13000 0x00 0x19000 0x00 0xe7000 0x00 0x114000 0x00 0xec000 0x00 0x201000 0x00 0x1000 0x00 0x203000 0x00 0x1000 0x00 0x205000 0x00 0x14fb000 0x00 0x1704000 0x00 0x8fc000 0x00 0x2014000 0x00 0x5fec000 0x00 0x8400000 0x00 0x3c00000 0x00 0x10000000 0x00 0x3000 0x00 0x10004000 0x00 0xc000 0x00 0x10011000 0x00 0x1f000 0x00 0x10034000 0x00 0x9fcc000 0x00 0x1a400000 0x00 0x5c00000>; + }; + + error-device@10003000 { + compatible = "sifive,error0"; + reg = <0x00 0x10003000 0x00 0x1000>; + phandle = <0x10>; + }; + + interrupt-controller@c000000 { + #interrupt-cells = <0x01>; + compatible = "sifive,plic-1.0.0"; + interrupt-controller; + interrupts-extended = <0x05 0xffffffff 0x05 0x09 0x08 0xffffffff 0x08 0x09 0x0b 0xffffffff 0x0b 0x09 0x0e 0xffffffff 0x0e 0x09>; + reg = <0x00 0xc000000 0x00 0x4000000>; + reg-names = "control"; + riscv,max-priority = <0x07>; + riscv,ndev = <0x208>; + phandle = <0x0f>; + }; + + order-obliterator@10030000 { + compatible = "sifive,order-obliterator0"; + interrupt-parent = <0x0f>; + interrupts = <0x204>; + reg = <0x00 0x10030000 0x00 0x4000>; + reg-names = "control"; + }; + + pl2@104000 { + cache-block-size = <0x40>; + cache-level = <0x02>; + cache-sets = <0x200>; + cache-size = <0x40000>; + cache-unified; + compatible = "sifive,pL2Cache0", "cache"; + next-level-cache = <0x14>; + reg = <0x00 0x104000 0x00 0x4000>; + reg-names = "control"; + sifive,ecc-granularity = <0x10>; + sifive,perfmon-counters = <0x06>; + phandle = <0x01>; + }; + + pl2@108000 { + cache-block-size = <0x40>; + cache-level = <0x02>; + cache-sets = <0x200>; + cache-size = <0x40000>; + cache-unified; + compatible = "sifive,pL2Cache0", "cache"; + next-level-cache = <0x14>; + reg = <0x00 0x108000 0x00 0x4000>; + reg-names = "control"; + sifive,ecc-granularity = <0x10>; + sifive,perfmon-counters = <0x06>; + phandle = <0x06>; + }; + + pl2@10c000 { + cache-block-size = <0x40>; + cache-level = <0x02>; + cache-sets = <0x200>; + cache-size = <0x40000>; + cache-unified; + compatible = "sifive,pL2Cache0", "cache"; + next-level-cache = <0x14>; + reg = <0x00 0x10c000 0x00 0x4000>; + reg-names = "control"; + sifive,ecc-granularity = <0x10>; + sifive,perfmon-counters = <0x06>; + phandle = <0x09>; + }; + + pl2@110000 { + cache-block-size = <0x40>; + cache-level = <0x02>; + cache-sets = <0x200>; + cache-size = <0x40000>; + cache-unified; + compatible = "sifive,pL2Cache0", "cache"; + next-level-cache = <0x14>; + reg = <0x00 0x110000 0x00 0x4000>; + reg-names = "control"; + sifive,ecc-granularity = <0x10>; + sifive,perfmon-counters = <0x06>; + phandle = <0x0c>; + }; + + rom@1a000000 { + compatible = "ucbbar,cacheable-zero0"; + reg = <0x00 0x1a000000 0x00 0x400000>; + phandle = <0x11>; + }; + + rom@3a000000 { + compatible = "ucbbar,cacheable-zero0"; + reg = <0x00 0x3a000000 0x00 0x400000>; + phandle = <0x12>; + }; + + subsystem_pbus_clock { + #clock-cells = <0x00>; + clock-frequency = <0x989680>; + clock-output-names = "subsystem_pbus_clock"; + compatible = "fixed-clock"; + }; + + teststatus@4000 { + compatible = "sifive,test0"; + reg = <0x00 0x4000 0x00 0x1000>; + reg-names = "control"; + }; + + tl-address-adjuster@20000000 { + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "sifive,tl-inter-sys-port", "sifive,tl-port", "simple-external-bus", "simple-bus"; + ranges = <0x20000000 0x00 0x20000000 0x1a000000 0x3a400000 0x00 0x3a400000 0x5c00000>; + sifive,port-width-bytes = <0x08>; + }; + + tl-inter-mem-master-port@80000000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "sifive,tl-inter-mem-master-port", "sifive,tl-port", "sifive,inter-mem-master-port", "simple-external-bus", "simple-bus"; + ranges = <0x00 0x80000000 0x00 0x80000000 0x7f 0x80000000>; + sifive,port-width-bytes = <0x20>; + }; + + trace-encoder-0@100000 { + compatible = "sifive,trace0"; + reg = <0x00 0x100000 0x00 0x1000>; + reg-names = "control"; + }; + + trace-encoder-1@101000 { + compatible = "sifive,trace0"; + reg = <0x00 0x101000 0x00 0x1000>; + reg-names = "control"; + }; + + trace-encoder-2@102000 { + compatible = "sifive,trace0"; + reg = <0x00 0x102000 0x00 0x1000>; + reg-names = "control"; + }; + + trace-encoder-3@103000 { + compatible = "sifive,trace0"; + reg = <0x00 0x103000 0x00 0x1000>; + reg-names = "control"; + }; + + trace-funnel-0@18000 { + compatible = "sifive,trace0"; + reg = <0x00 0x18000 0x00 0x1000>; + reg-names = "control"; + }; + + serial@0x50900000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00 0x50900000 0x00 0x10000>; + clock-frequency = <0xbebc200>; + interrupt-parent = <0x0f>; + interrupts = <0x64>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + numa-node-id = <0x00>; + status = "okay"; + }; + + serial@0x50910000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00 0x50910000 0x00 0x10000>; + clock-frequency = <0xbebc200>; + interrupt-parent = <0x0f>; + interrupts = <0x65>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + numa-node-id = <0x00>; + status = "okay"; + }; + + serial@0x50920000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00 0x50920000 0x00 0x10000>; + clock-frequency = <0xbebc200>; + interrupt-parent = <0x0f>; + interrupts = <0x66>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + numa-node-id = <0x00>; + status = "okay"; + }; + + serial@0x50930000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00 0x50930000 0x00 0x10000>; + clock-frequency = <0xbebc200>; + interrupt-parent = <0x0f>; + interrupts = <0x67>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + numa-node-id = <0x00>; + status = "disabled"; + }; + + serial@0x50940000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00 0x50940000 0x00 0x10000>; + clock-frequency = <0xbebc200>; + interrupt-parent = <0x0f>; + interrupts = <0x68>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + numa-node-id = <0x00>; + status = "disabled"; + }; + + scu_sys_con@0x51810000 { + compatible = "eswin,eic7700-scu-sys-con", "syscon", "simple-mfd"; + #syscon-cells = <0x02>; + #size-cells = <0x02>; + reg = <0x00 0x51810000 0x00 0x8000>; + numa-node-id = <0x00>; + phandle = <0x16>; + + noc@51810324 { + compatible = "eswin,eic7700-noc-wdt"; + interrupt-parent = <0x0f>; + interrupts = <0x188 0x189 0x18a 0x18b 0x18c 0x18d 0x18e 0x18f 0x190 0x191 0x192 0x193 0x194 0x195 0x196 0x197 0x198 0x199 0x19a 0x19b 0x19c 0x19d 0x19e 0x19f 0x1a0 0x1a1 0x1a2 0x1a3 0x1a4 0x1a5 0x1a6 0x1a7 0x1a8 0x1a9 0x1aa>; + eswin,syscrg_csr = <0x15 0x100 0xffff>; + status = "okay"; + }; + }; + + sys-crg@51828000 { + compatible = "eswin,eic7700-sys-crg", "syscon", "simple-mfd"; + reg = <0x00 0x51828000 0x00 0x80000>; + numa-node-id = <0x00>; + phandle = <0x15>; + + reset-controller { + compatible = "eswin,eic7700-reset"; + #reset-cells = <0x02>; + status = "okay"; + phandle = <0x17>; + }; + + clock-controller { + compatible = "eswin,eic7700-clock"; + #clock-cells = <0x01>; + status = "okay"; + phandle = <0x03>; + }; + }; + + hfclk { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0xbebc200>; + clock-output-names = "hfclk"; + }; + + hsp_sp_top_csr@0x50440000 { + compatible = "eswin,eic7700-hsp-sp-csr", "syscon"; + #size-cells = <0x02>; + reg = <0x00 0x50440000 0x00 0x2000>; + phandle = <0x19>; + }; + + iommu@50c00000 { + compatible = "arm,smmu-v3"; + reg = <0x00 0x50c00000 0x00 0x100000>; + eswin,syscfg = <0x16 0x3fc>; + interrupt-parent = <0x0f>; + interrupts = <0x164 0x168 0x165 0x166>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <0x01>; + resets = <0x17 0x05 0x01 0x17 0x05 0x02 0x17 0x05 0x10 0x17 0x05 0x20 0x17 0x05 0x40 0x17 0x05 0x80 0x17 0x05 0x100 0x17 0x05 0x200 0x17 0x05 0x400 0x17 0x05 0x800>; + reset-names = "axi_rst", "cfg_rst", "tbu0_rst", "tbu1_rst", "tbu2_rst", "tbu3_rst", "tbu4_rst", "tbu5_rst", "tbu6_rst", "tbu7_rst"; + status = "okay"; + numa-node-id = <0x00>; + phandle = <0x18>; + }; + + pmu@50c02000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x00 0x50c02000 0x00 0x1000 0x00 0x50c22000 0x00 0x1000>; + eswin,syscfg = <0x16 0x3fc>; + interrupt-parent = <0x0f>; + interrupts = <0x16b>; + status = "disabled"; + numa-node-id = <0x00>; + }; + + power-controller@51808000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "eswin,eic7700-pmu-controller"; + reg = <0x00 0x51808000 0x00 0x8000>; + numa-node-id = <0x00>; + status = "okay"; + + eic7700-pmu-controller-port@0 { + compatible = "eswin,eic7700-pmu-controller-port"; + reg_base = <0x00>; + power_status = <0x01>; + power_delay = <0x06 0x06 0x03 0x03>; + clock_delay = <0x04 0x02 0x02 0x02>; + reset_delay = <0x02 0x04 0x02 0x02>; + clamp_delay = <0x03 0x03 0x02 0x02>; + label = "D0_PCIE"; + tbus = <0x03>; + }; + + eic7700-pmu-controller-port@40 { + compatible = "eswin,eic7700-pmu-controller-port"; + reg_base = <0x40>; + power_status = <0x01>; + power_delay = <0x06 0x06 0x03 0x03>; + clock_delay = <0x04 0x02 0x02 0x02>; + reset_delay = <0x02 0x04 0x02 0x02>; + clamp_delay = <0x03 0x03 0x02 0x02>; + tbus = <0x71>; + label = "D0_DSP1"; + }; + + eic7700-pmu-controller-port@80 { + compatible = "eswin,eic7700-pmu-controller-port"; + reg_base = <0x80>; + power_status = <0x01>; + power_delay = <0x06 0x06 0x03 0x03>; + clock_delay = <0x04 0x02 0x02 0x02>; + reset_delay = <0x02 0x04 0x02 0x02>; + clamp_delay = <0x03 0x03 0x02 0x02>; + tbus = <0x00 0x00>; + label = "D0_VI"; + }; + + eic7700-pmu-controller-port@c0 { + compatible = "eswin,eic7700-pmu-controller-port"; + reg_base = <0xc0>; + power_status = <0x01>; + power_delay = <0x06 0x06 0x03 0x03>; + clock_delay = <0x04 0x02 0x02 0x02>; + reset_delay = <0x02 0x04 0x02 0x02>; + clamp_delay = <0x03 0x03 0x02 0x02>; + label = "D0_VO"; + }; + + eic7700-pmu-controller-port@140 { + compatible = "eswin,eic7700-pmu-controller-port"; + reg_base = <0x140>; + power_status = <0x01>; + power_delay = <0x06 0x06 0x03 0x03>; + clock_delay = <0x04 0x02 0x02 0x02>; + reset_delay = <0x02 0x04 0x02 0x02>; + clamp_delay = <0x03 0x03 0x02 0x02>; + tbus = <0x10 0x13 0x11 0x12>; + label = "D0_CODEC"; + }; + + eic7700-pmu-controller-port@200 { + compatible = "eswin,eic7700-pmu-controller-port"; + reg_base = <0x200>; + power_status = <0x01>; + power_delay = <0x06 0x06 0x03 0x03>; + clock_delay = <0x04 0x02 0x02 0x02>; + reset_delay = <0x02 0x04 0x02 0x02>; + clamp_delay = <0x03 0x03 0x02 0x02>; + tbus = <0x72>; + label = "D0_DSP2"; + }; + + eic7700-pmu-controller-port@240 { + compatible = "eswin,eic7700-pmu-controller-port"; + reg_base = <0x240>; + power_status = <0x01>; + power_delay = <0x06 0x06 0x03 0x03>; + clock_delay = <0x04 0x02 0x02 0x02>; + reset_delay = <0x02 0x04 0x02 0x02>; + clamp_delay = <0x03 0x03 0x02 0x02>; + tbus = <0x73>; + label = "D0_DSP3"; + }; + }; + + dma-controller-hsp@0x50430000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x00 0x50430000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0x39>; + #dma-cells = <0x02>; + clocks = <0x03 0x2b2>; + clock-names = "core-clk"; + resets = <0x17 0x07 0x4000 0x17 0x07 0x100000>; + reset-names = "arst", "prst"; + dma-channels = <0x0c>; + snps,dma-masters = <0x01>; + snps,priority = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b>; + snps,data-width = <0x02>; + snps,block-size = <0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000>; + snps,axi-max-burst-len = <0x10>; + snps,max-msize = <0x40>; + iommus = <0x18 0x01>; + tbus = <0x02>; + eswin,hsp_sp_csr = <0x19 0x104c>; + eswin,syscfg = <0x16 0x3004 0x370>; + numa-node-id = <0x00>; + status = "okay"; + }; + + dma-controller-aon@0x518c0000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x00 0x518c0000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0x121>; + #dma-cells = <0x02>; + clocks = <0x03 0x266>; + clock-names = "core-clk"; + resets = <0x17 0x27 0x01 0x17 0x27 0x02>; + reset-names = "arst", "prst"; + dma-channels = <0x10>; + snps,dma-masters = <0x02>; + snps,priority = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f>; + snps,data-width = <0x03>; + snps,block-size = <0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000 0x80000>; + snps,axi-max-burst-len = <0x20>; + snps,max-msize = <0x40>; + #size-cells = <0x02>; + #address-cells = <0x02>; + dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x100 0x00>; + iommus = <0x18 0x1a>; + tbus = <0x04>; + eswin,syscfg = <0x16 0x3004 0x370>; + numa-node-id = <0x00>; + status = "okay"; + phandle = <0x27>; + }; + + ethernet@50400000 { + compatible = "eswin,eic7700-qos-eth"; + reg = <0x00 0x50400000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupt-names = "macirq"; + interrupts = <0x3d>; + phy-mode = "rgmii"; + numa-node-id = <0x00>; + id = <0x00>; + status = "okay"; + clocks = <0x03 0x226 0x03 0x227 0x03 0x228>; + clock-names = "app", "stmmaceth", "tx"; + resets = <0x17 0x07 0x4000000>; + reset-names = "ethrst"; + tbus = <0x02>; + eswin,hsp_sp_csr = <0x19 0x1030 0x100 0x108>; + eswin,syscrg_csr = <0x15 0x148 0x14c>; + snps,axi-config = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <0x1b>; + rst-gpios = <0x1c 0x0a 0x01>; + eswin,rgmiisel = <0x1d 0x290 0x03>; + eswin,led-cfgs = <0x6100 0xa40 0x420>; + + stmmac-axi-config { + snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; + snps,rd_osr_lmt = <0x02>; + snps,wr_osr_lmt = <0x02>; + snps,lpi_en = <0x00>; + phandle = <0x1a>; + }; + }; + + ethernet@50410000 { + compatible = "eswin,eic7700-qos-eth"; + reg = <0x00 0x50410000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupt-names = "macirq"; + interrupts = <0x46>; + phy-mode = "rgmii"; + numa-node-id = <0x00>; + id = <0x01>; + status = "okay"; + clocks = <0x03 0x226 0x03 0x227 0x03 0x229>; + clock-names = "app", "stmmaceth", "tx"; + resets = <0x17 0x07 0x2000000>; + reset-names = "ethrst"; + tbus = <0x02>; + eswin,hsp_sp_csr = <0x19 0x1034 0x200 0x208>; + eswin,syscrg_csr = <0x15 0x148 0x14c>; + snps,axi-config = <0x1e>; + pinctrl-names = "default"; + pinctrl-0 = <0x1f>; + rst-gpios = <0x1c 0x0f 0x01>; + eswin,rgmiisel = <0x1d 0x294 0x03>; + eswin,led-cfgs = <0x6100 0xa40 0x420>; + + stmmac-axi-config { + snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; + snps,rd_osr_lmt = <0x02>; + snps,wr_osr_lmt = <0x02>; + snps,lpi_en = <0x00>; + phandle = <0x1e>; + }; + }; + + noc { + compatible = "eswin,noc", "simple-bus"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + d0_cfg_noc { + compatible = "eswin,eic7700-noc"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + reg = <0x00 0x52060000 0x00 0x4000>; + interrupts = <0x1be>; + interrupt-names = "error"; + interrupt-parent = <0x0f>; + errlogger,idx = <0x00 0x01 0x03 0x05>; + status = "okay"; + + sideband_manager@52061000 { + compatible = "eswin,win2xxx-noc-sideband-manager"; + reg = <0x00 0x52061000 0x00 0x10>; + SenseIn0 = <0x1e 0x00 0x1f 0x01 0x20 0x02 0x21 0x03 0x22 0x04 0x23 0x05 0x24 0x06 0x25 0x07 0x26 0x08 0x27 0x09 0x28 0x0a 0x29 0x0b 0x2a 0x0c 0x2b 0x0d 0x2c 0x0e 0x2d 0x0f 0x2e 0x10 0x2f 0x11 0x30 0x12 0x31 0x13 0x32 0x14>; + bf-name = "SBM_CLMM", "SBM_CNOC_AON", "SBM_CNOC_DDRT0_CTRL", "SBM_CNOC_DDRT0_PHY ", "SBM_CNOC_DDRT1_CTRL", "SBM_CNOC_DDRT1_PHY", "SBM_CNOC_DSPT", "SBM_CNOC_GPU", "SBM_CNOC_HSP", "SBM_CNOC_LSP_APB2", "SBM_CNOC_LSP_APB3", "SBM_CNOC_LSP_APB4", "SBM_CNOC_LSP_APB6", "SBM_CNOC_MCPUT_D2D", "SBM_CNOC_NPU", "SBM_CNOC_PCIET_P", "SBM_CNOC_PCIET_X", "SBM_CNOC_TCU", "SBM_CNOC_VC", "SBM_CNOC_VI", "SBM_CNOC_VO"; + }; + + ErrorLogger0 { + compatible = "eswin,eic7700,register"; + offset,length = <0x14 0x20>; + description = "Register 0 to log errors"; + + lock { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x01>; + lut = "Not Locked", "Locked"; + }; + + OpCode { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x01 0x04>; + lut = "RD: data read with incrementing address", "RDW: data read with wrapping address", "RDL: allocates monitor in the Target with incrementing address", "RDX: exclusive read with incrementing address", "WR: data write with incrementing address", "WRW: data write with wrapping address", "WRC: conditional write if matching monitor in Target is found", "RSV: reserved", "PRE: preamble packet of linked sequence (locked sequence)", "URG: urgency packet used for QoS (status must be REQ)"; + }; + + ErrCode { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x08 0x03>; + lut = "SLV (error source: Target): error detected by the Slave without any information or no Error", "DEC (error source: Initiator NIU): decode error", "UNS (error source: Target NIU): unsupported access type", "DISC (error source: Power Disconnect): disconnected Target or NoC domain", "SEC (error source: Initiator NIU or Firewall): security error", "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator", "TMO (error source: Target NIU): time-out", "RSV: reserved"; + }; + + Len1 { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x10 0x0c>; + }; + + Format { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x1f 0x01>; + lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)"; + }; + }; + + ErrorLogger1 { + compatible = "eswin,eic7700,register", "eswin,eic7700,noc,filter,routeid"; + offset,length = <0x18 0x20>; + description = "Register 1 to log errors"; + + InitFlow { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x0f 0x01>; + lut = "snoc_cnoc/I/0"; + }; + + TargetFlow { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x0a 0x05>; + lut = "clmm/T/0", "cnoc_aon/T/0", "cnoc_ddrt0_ctrl/T/0", "cnoc_ddrt0_phy/T/0", "cnoc_ddrt1_ctrl/T/0", "cnoc_ddrt1_phy/T/0", "cnoc_dspt/T/0", "cnoc_gpu/T/0", "cnoc_hsp/T/0", "cnoc_lsp_apb2/T/0", "cnoc_lsp_apb3/T/0", "cnoc_lsp_apb4/T/0", "cnoc_lsp_apb6/T/0", "cnoc_mcput_d2d/T/0", "cnoc_npu/T/0", "cnoc_pciet_p/T/0", "cnoc_pciet_x/T/0", "cnoc_service/T/0", "cnoc_tcu/T/0", "cnoc_vc/T/0", "cnoc_vi/T/0", "cnoc_vo/T/0", "RESERVED", "RESERVED", "RESERVED", "RESERVED", "RESERVED", "RESERVED", "RESERVED", "RESERVED", "RESERVED", "RESERVED"; + }; + + TargetSubRange { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x08 0x02>; + }; + + SeqId { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x08>; + }; + }; + + ErrorLogger3 { + compatible = "eswin,eic7700,register"; + offset,length = <0x20 0x20>; + description = "Register 3 to log errors"; + aperture-link = <0x01>; + + AbsoluteAddress { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x08 0x08>; + aperture-size = <0x2e>; + aperture-idx,aperture-base = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x51600000 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x71600000 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x51800000 0x00 0x00 0x00 0x01 0x00 0x01 0x00 0x71800000 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x52300000 0x00 0x00 0x00 0x02 0x00 0x01 0x00 0x72300000 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x53000000 0x00 0x00 0x00 0x03 0x00 0x01 0x00 0x73000000 0x00 0x00 0x00 0x04 0x00 0x00 0x00 0x52380000 0x00 0x00 0x00 0x04 0x00 0x01 0x00 0x72380000 0x00 0x00 0x00 0x05 0x00 0x00 0x00 0x53800000 0x00 0x00 0x00 0x05 0x00 0x01 0x00 0x73800000 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x52200000 0x00 0x00 0x00 0x06 0x00 0x01 0x00 0x72200000 0x00 0x00 0x00 0x07 0x00 0x00 0x00 0x51400000 0x00 0x00 0x00 0x07 0x00 0x01 0x00 0x71400000 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x50400000 0x00 0x00 0x00 0x08 0x00 0x01 0x00 0x70400000 0x00 0x00 0x00 0x09 0x00 0x00 0x00 0x50800000 0x00 0x00 0x00 0x09 0x00 0x01 0x00 0x70800000 0x00 0x00 0x00 0x0a 0x00 0x00 0x00 0x50900000 0x00 0x00 0x00 0x0a 0x00 0x01 0x00 0x70900000 0x00 0x00 0x00 0x0b 0x00 0x00 0x00 0x50a00000 0x00 0x00 0x00 0x0b 0x00 0x01 0x00 0x70a00000 0x00 0x00 0x00 0x0c 0x00 0x00 0x00 0x50b00000 0x00 0x00 0x00 0x0c 0x00 0x01 0x00 0x70b00000 0x00 0x00 0x00 0x0d 0x00 0x00 0x00 0x52100000 0x00 0x00 0x00 0x0d 0x00 0x01 0x00 0x72100000 0x00 0x00 0x00 0x0e 0x00 0x00 0x00 0x51c00000 0x00 0x00 0x00 0x0e 0x00 0x01 0x00 0x71c00000 0x00 0x00 0x00 0x0f 0x00 0x00 0x00 0x50000000 0x00 0x00 0x00 0x0f 0x00 0x01 0x00 0x70000000 0x00 0x00 0x00 0x10 0x00 0x00 0x00 0x54000000 0x00 0x00 0x00 0x10 0x00 0x01 0x00 0x74000000 0x00 0x00 0x00 0x11 0x00 0x00 0x00 0x52060000 0x00 0x00 0x00 0x11 0x00 0x01 0x00 0x72060000 0x00 0x00 0x00 0x12 0x00 0x00 0x00 0x50c00000 0x00 0x00 0x00 0x12 0x00 0x01 0x00 0x70c00000 0x00 0x00 0x00 0x13 0x00 0x00 0x00 0x50100000 0x00 0x00 0x00 0x13 0x00 0x01 0x00 0x70100000 0x00 0x00 0x00 0x14 0x00 0x00 0x00 0x51000000 0x00 0x00 0x00 0x14 0x00 0x01 0x00 0x71000000 0x00 0x00 0x00 0x15 0x00 0x00 0x00 0x50200000 0x00 0x00 0x00 0x15 0x00 0x01 0x00 0x70200000>; + }; + }; + + ErrorLogger5 { + compatible = "eswin,eic7700,register"; + offset,length = <0x28 0x20>; + description = "Register 5 to log errors"; + + User_flag { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x07>; + lut = "Cache_0", "Cache_1", "Cache_2", "Cache_3", "Prot_0", "Prot_1", "Prot_2"; + }; + }; + }; + + d0_llc_noc@52081400 { + compatible = "eswin,eic7700-noc"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + reg = <0x00 0x52081400 0x00 0x4000>; + interrupts = <0x1b9>; + interrupt-names = "error"; + interrupt-parent = <0x0f>; + errlogger,idx = <0x00 0x01 0x03 0x04 0x05>; + status = "okay"; + stat,0 = "TracePort:ddr0_p0_req"; + stat,1 = "TracePort:ddr1_p0_req"; + + sideband_manager@52082000 { + compatible = "eswin,win2xxx-noc-sideband-manager"; + reg = <0x00 0x52082000 0x00 0x10>; + SenseIn0 = <0x3c 0x00 0x3d 0x01 0x3e 0x02 0x3f 0x03>; + bf-name = "SBM_LNOC_NPU_LLC0", "SBM_LNOC_NPU_LLC1", "SBM_LNOC_DDRT0_P0", "SBM_LNOC_DDRT1_P0"; + }; + + llcnoc_packet_ddr0_p0_req_probe@52080000 { + compatible = "eswin,win2xxx-noc-packet-probe"; + reg = <0x00 0x52080000 0x00 0x4000>; + clocks = <0x03 0x217>; + clock-names = "clk"; + interrupts = <0x1bd>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x01>; + counter,nr = <0x02>; + portsel = "ddr0_p0_req"; + }; + + llcnoc_packet_ddr1_p0_req_probe@52080800 { + compatible = "eswin,win2xxx-noc-packet-probe"; + reg = <0x00 0x52080800 0x00 0x4000>; + clocks = <0x03 0x21c>; + clock-names = "clk"; + interrupts = <0x1bb>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x01>; + counter,nr = <0x02>; + portsel = "ddr1_p0_req"; + }; + + llcnoc_trans_probe@52081000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + compatible = "eswin,win2xxx-noc-trans-probe"; + reg = <0x00 0x52081000 0x00 0x4000>; + clocks = <0x03 0x203>; + clock-names = "clk"; + interrupts = <0x1b9>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x02>; + counter,nr = <0x08>; + profiler,nr = <0x01>; + portsel = "npu_llc0", "npu_llc1"; + + llcnoc_trans_npu_llc0_filter@52081480 { + status = "disabled"; + compatible = "eswin,win2xxx-noc-trans-filter"; + reg = <0x00 0x52081480 0x00 0x80>; + }; + + llcnoc_trans_npu_llc1_filter@52081500 { + status = "disabled"; + compatible = "eswin,win2xxx-noc-trans-filter"; + reg = <0x00 0x52081500 0x00 0x80>; + }; + + llcnoc_trans_profiler@52081580 { + compatible = "eswin,win2xxx-noc-trans-profiler"; + reg = <0x00 0x52081580 0x00 0x80>; + }; + }; + + ErrorLogger0 { + compatible = "eswin,eic7700,register"; + offset,length = <0x14 0x20>; + description = "Register 0 to log errors"; + + lock { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x01>; + lut = "Not Locked", "Locked"; + }; + + OpCode { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x01 0x04>; + lut = "RD: data read with incrementing address", "RDW: data read with wrapping address", "RDL: allocates monitor in the Target with incrementing address", "RDX: exclusive read with incrementing address", "WR: data write with incrementing address", "WRW: data write with wrapping address", "WRC: conditional write if matching monitor in Target is found", "RSV: reserved", "PRE: preamble packet of linked sequence (locked sequence)", "URG: urgency packet used for QoS (status must be REQ)"; + }; + + ErrCode { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x08 0x03>; + lut = "SLV (error source: Target): error detected by the Slave without any information or no Error", "DEC (error source: Initiator NIU): decode error", "UNS (error source: Target NIU): unsupported access type", "DISC (error source: Power Disconnect): disconnected Target or NoC domain", "SEC (error source: Initiator NIU or Firewall): security error", "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator", "TMO (error source: Target NIU): time-out", "RSV: reserved"; + }; + + Len1 { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x10 0x0c>; + }; + + Format { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x1f 0x01>; + lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)"; + }; + }; + + ErrorLogger1 { + compatible = "eswin,eic7700,register", "eswin,eic7700,noc,filter,routeid"; + offset,length = <0x18 0x20>; + description = "Register 1 to log errors"; + + InitFlow { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x0e 0x02>; + lut = "npu_lnoc_llc0/I/0", "npu_lnoc_llc1/I/0", "snoc_lnoc/I/0", "RESERVED"; + }; + + TargetFlow { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x0c 0x02>; + lut = "lnoc_ddrt0_p0/T/0", "lnoc_ddrt1_p0/T/0", "lnoc_service/T/0", "RESERVED"; + }; + + TargetSubRange { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x08 0x04>; + }; + + SeqId { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x08>; + }; + }; + + ErrorLogger3 { + compatible = "eswin,eic7700,register"; + offset,length = <0x20 0x20>; + description = "Register 3 to log errors"; + aperture-link = <0x01>; + msb-link = <0x04>; + + AbsoluteAddress { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x08 0x08>; + aperture-size = <0x35>; + aperture-idx,aperture-base = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0xc0 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0xe0 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x09 0x40 0x100 0x00 0x00 0x00 0x00 0x00 0x0a 0x100 0x00 0x00 0x00 0x00 0x00 0x00 0x0b 0x100 0x100 0x00 0x00 0x00 0x00 0x00 0x0c 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x00 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x00 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x00 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x00 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x00 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x00 0x00 0x01 0x00 0x06 0xc0 0x80 0x00 0x00 0x00 0x01 0x00 0x07 0xe0 0x80 0x00 0x00 0x00 0x01 0x00 0x08 0x40 0x80 0x00 0x00 0x00 0x01 0x00 0x09 0x40 0x180 0x00 0x00 0x00 0x01 0x00 0x0a 0x100 0x80 0x00 0x00 0x00 0x01 0x00 0x0b 0x100 0x180 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x01 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x01 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x01 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x01 0x00 0x00 0x00 0x06 0xc0 0x00 0x00 0x01 0x00 0x00 0x00 0x07 0xe0 0x00 0x00 0x01 0x00 0x00 0x00 0x08 0x40 0x00 0x00 0x01 0x00 0x00 0x00 0x09 0x40 0x100 0x00 0x01 0x00 0x00 0x00 0x0a 0x100 0x00 0x00 0x01 0x00 0x00 0x00 0x0b 0x100 0x100 0x00 0x01 0x00 0x00 0x00 0x0c 0x00 0x00 0x00 0x01 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x01 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x01 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x01 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x01 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x01 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x01 0x00 0x01 0x00 0x06 0xc0 0x80 0x00 0x01 0x00 0x01 0x00 0x07 0xe0 0x80 0x00 0x01 0x00 0x01 0x00 0x08 0x40 0x80 0x00 0x01 0x00 0x01 0x00 0x09 0x40 0x180 0x00 0x01 0x00 0x01 0x00 0x0a 0x100 0x80 0x00 0x01 0x00 0x01 0x00 0x0b 0x100 0x180 0x00 0x02 0x00 0x02 0x00 0x00 0x00 0x52080000 0x00 0x02 0x00 0x02 0x00 0x01 0x00 0x72080000 0x00 0x02 0x00 0x02 0x00 0x02 0x00 0x00>; + }; + }; + + ErrorLogger4 { + compatible = "eswin,eic7700,register"; + offset,length = <0x24 0x20>; + description = "Register 4 to log errors"; + + addr_msb { + compatible = "eswin,eic7700,bitfield"; + description = "Stores NTTP packet header field Addr (MSBs) of the logged error"; + offset,length = <0x00 0x09>; + }; + }; + + ErrorLogger5 { + compatible = "eswin,eic7700,register"; + offset,length = <0x28 0x20>; + description = "Register 5 to log errors"; + + User_flag { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x10>; + lut = "Cache_0", "Cache_1", "Cache_2", "Cache_3", "Prot_0", "Prot_1", "Prot_2", "Qos_0", "Qos_1", "Qos_2", "Qos_3", "User_0", "User_1", "User_2", "User_3", "User_4"; + }; + }; + }; + + d0_sys_noc@52002C00 { + compatible = "eswin,eic7700-noc"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + reg = <0x00 0x52002c00 0x00 0x4000>; + interrupts = <0x1af>; + interrupt-names = "error"; + interrupt-parent = <0x0f>; + errlogger,idx = <0x00 0x01 0x03 0x04 0x05>; + eswin,qos-configs = "DSPT", "NPU", "SPISLV_TBU3"; + eswin,DSPT-qos-base = <0x52002c80>; + eswin,DSPT-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x03 0x14 0x01 0x18 0x01>; + eswin,NPU-qos-base = "R", "-"; + eswin,NPU-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>; + eswin,SPISLV_TBU3-qos-base = <0x52002d80>; + eswin,SPISLV_TBU3-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>; + status = "okay"; + stat,0 = "TracePort:ddr0_p1_req", "InitFlow:mcput_snoc_mp/I/0"; + stat,1 = "TracePort:ddr0_p2_req", "InitFlow:dspt_snoc/I/0", "AddrBase:0x81000000", "AddrSize:0x30", "Opcode:RdWrLockUrg", "Status:ReqRsp", "Length:0x8000", "Urgency:0x0"; + stat,2 = "TracePort:ddr1_p1_req", "Status:Req", "AddrSize:0x28"; + stat,3 = "TracePort:ddr1_p2_req"; + latency,0 = "TracePort:sysnoc_trans_probe_0", "AddrSize:0x0"; + latency,1 = "TracePort:sysnoc_trans_probe_1", "Mode:latency", "AddrBase:0x82000000", "AddrSize:0x28", "Opcode:RdWr"; + pending,0 = "TracePort:sysnoc_trans_probe_2", "AddrSize:0x3"; + + sideband_manager@52004000 { + compatible = "eswin,win2xxx-noc-sideband-manager"; + reg = <0x00 0x52004000 0x00 0x10>; + SenseIn0 = <0x00 0x00 0x01 0x01 0x02 0x02 0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06 0x07 0x07 0x08 0x08 0x09 0x09 0x0a 0x0a 0x0b 0x0b 0x0c 0x0c 0x0d 0x0d 0x0e 0x0e 0x0f 0x0f 0x10 0x10 0x11 0x11 0x12 0x12 0x13 0x13 0x14 0x14 0x15 0x15>; + bf-name = "SBM_AON_SNOC_SP0", "SBM_DSPT_SNOC", "SBM_JTAG_SNOC", "SBM_MCPUT_SNOC_D2D ", "SBM_MCPUT_SNOC_MP", "SBM_MCPUT_SNOC_SP0", "SBM_MCPUT_SNOC_SP1", "SBM_NPU_SNOC_SP0", "SBM_NPU_SNOC_SP1", "SBM_PCIET_SNOC_P", "SBM_SPISLV_PCIET_SNOC", "SBM_TBU4_SNOC", "SBM_TCU_SNOC", "SBM_SNOC_AON", "SBM_SNOC_DDR0_P1", "SBM_SNOC_DDR0_P2", "SBM_SNOC_DDR1_P1", "SBM_SNOC_DDR1_P2", "SBM_SNOC_DSPT", "SBM_SNOC_MCPUT_D2D", "SBM_SNOC_NPU", "SBM_SNOC_PCIET"; + }; + + sysnoc_packet_ddr0_p1_req_probe@52000000 { + compatible = "eswin,win2xxx-noc-packet-probe"; + reg = <0x00 0x52000000 0x00 0x4000>; + clocks = <0x03 0x218>; + clock-names = "clk"; + interrupts = <0x1b7>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x01>; + counter,nr = <0x02>; + portsel = "ddr0_p1_req"; + }; + + sysnoc_packet_ddr0_p2_req_probe@52000800 { + compatible = "eswin,win2xxx-noc-packet-probe"; + reg = <0x00 0x52000800 0x00 0x4000>; + clocks = <0x03 0x219>; + clock-names = "clk"; + interrupts = <0x1b5>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x01>; + counter,nr = <0x02>; + portsel = "ddr0_p2_req"; + }; + + sysnoc_packet_ddr1_p1_req_probe@52001000 { + compatible = "eswin,win2xxx-noc-packet-probe"; + reg = <0x00 0x52001000 0x00 0x4000>; + clocks = <0x03 0x21d>; + clock-names = "clk"; + interrupts = <0x1b3>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x01>; + counter,nr = <0x02>; + portsel = "ddr1_p1_req"; + }; + + sysnoc_packet_ddr1_p2_req_probe@52001800 { + compatible = "eswin,win2xxx-noc-packet-probe"; + reg = <0x00 0x52001800 0x00 0x4000>; + clocks = <0x03 0x21e>; + clock-names = "clk"; + interrupts = <0x1b1>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x01>; + counter,nr = <0x02>; + portsel = "ddr1_p2_req"; + }; + + sysnoc_trans_probe_0@52002000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + compatible = "eswin,win2xxx-noc-trans-probe"; + reg = <0x00 0x52002000 0x00 0x4000>; + clocks = <0x03 0x203>; + clock-names = "clk"; + interrupts = <0x1ae>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x02>; + counter,nr = <0x08>; + profiler,nr = <0x01>; + portsel = "dspt_snoc", "npu_sp1"; + + sysnoc_trans_dspt_filter@52002E00 { + status = "disabled"; + compatible = "eswin,win2xxx-noc-trans-filter"; + reg = <0x00 0x52002e00 0x00 0x80>; + }; + + sysnoc_trans_npu_sp1_filter@52002F80 { + status = "disabled"; + compatible = "eswin,win2xxx-noc-trans-filter"; + reg = <0x00 0x52002f80 0x00 0x80>; + }; + + sysnoc_trans_profiler@52003180 { + compatible = "eswin,win2xxx-noc-trans-profiler"; + reg = <0x00 0x52003180 0x00 0x80>; + }; + }; + + sysnoc_trans_probe_1@52002400 { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + compatible = "eswin,win2xxx-noc-trans-probe"; + reg = <0x00 0x52002400 0x00 0x4000>; + clocks = <0x03 0x203>; + clock-names = "clk"; + interrupts = <0x1ad>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x03>; + counter,nr = <0x0c>; + profiler,nr = <0x01>; + portsel = "mcput_mp", "mcput_sp1", "tcu"; + + sysnoc_trans_mcput_mp_filter@52002E80 { + status = "okay"; + compatible = "eswin,win2xxx-noc-trans-filter"; + reg = <0x00 0x52002e80 0x00 0x80>; + }; + + sysnoc_trans_mcput_sp1_filter@52002F00 { + status = "okay"; + compatible = "eswin,win2xxx-noc-trans-filter"; + reg = <0x00 0x52002f00 0x00 0x80>; + }; + + sysnoc_trans_tcu_filter@52003100 { + status = "okay"; + compatible = "eswin,win2xxx-noc-trans-filter"; + reg = <0x00 0x52003100 0x00 0x80>; + }; + + sysnoc_trans_profiler@52003200 { + compatible = "eswin,win2xxx-noc-trans-profiler"; + reg = <0x00 0x52003200 0x00 0x80>; + }; + }; + + sysnoc_trans_probe_2@52002800 { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + compatible = "eswin,win2xxx-noc-trans-probe"; + reg = <0x00 0x52002800 0x00 0x4000>; + clocks = <0x03 0x203>; + clock-names = "clk"; + interrupts = <0x1ac>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x02>; + counter,nr = <0x08>; + profiler,nr = <0x01>; + portsel = "spislv_tbu3", "tbu4_snoc"; + + sysnoc_trans_spislv_tbu3_filter@52003000 { + status = "disabled"; + compatible = "eswin,win2xxx-noc-trans-filter"; + reg = <0x00 0x52003000 0x00 0x80>; + }; + + sysnoc_trans_tbu4_filter@52003080 { + status = "disabled"; + compatible = "eswin,win2xxx-noc-trans-filter"; + reg = <0x00 0x52003080 0x00 0x80>; + }; + + sysnoc_trans_profiler@52003280 { + compatible = "eswin,win2xxx-noc-trans-profiler"; + reg = <0x00 0x52003280 0x00 0x80>; + }; + }; + + ErrorLogger0 { + compatible = "eswin,eic7700,register"; + offset,length = <0x14 0x20>; + description = "Register 0 to log errors"; + + lock { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x01>; + lut = "Not Locked", "Locked"; + }; + + OpCode { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x01 0x04>; + lut = "RD: data read with incrementing address", "RDW: data read with wrapping address", "RDL: allocates monitor in the Target with incrementing address", "RDX: exclusive read with incrementing address", "WR: data write with incrementing address", "WRW: data write with wrapping address", "WRC: conditional write if matching monitor in Target is found", "RSV: reserved", "PRE: preamble packet of linked sequence (locked sequence)", "URG: urgency packet used for QoS (status must be REQ)"; + }; + + ErrCode { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x08 0x03>; + lut = "SLV (error source: Target): error detected by the Slave without any information or no Error", "DEC (error source: Initiator NIU): decode error", "UNS (error source: Target NIU): unsupported access type", "DISC (error source: Power Disconnect): disconnected Target or NoC domain", "SEC (error source: Initiator NIU or Firewall): security error", "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator", "TMO (error source: Target NIU): time-out", "RSV: reserved"; + }; + + Len1 { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x10 0x0c>; + }; + + Format { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x1f 0x01>; + lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)"; + }; + }; + + ErrorLogger1 { + compatible = "eswin,eic7700,register", "eswin,eic7700,noc,filter,routeid"; + offset,length = <0x18 0x20>; + description = "Register 1 to log errors"; + + InitFlow { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x13 0x04>; + lut = "aon_snoc_sp0/I/0", "dspt_snoc/I/0", "jtag_snoc/I/0", "mcput_snoc_d2d/I/0", "mcput_snoc_mp/I/0", "mcput_snoc_sp0/I/0", "mcput_snoc_sp1/I/0", "mnoc_snoc/I/0", "npu_snoc_sp0/I/0", "npu_snoc_sp1/I/0", "pciet_snoc_p/I/0", "rnoc_snoc/I/0", "spislv_tbu3_snoc/I/0", "tbu4_snoc/I/0", "tcu_snoc/I/0", "RESERVED0"; + }; + + TargetFlow { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x0f 0x04>; + lut = "snoc_aon/T/0", "snoc_cnoc/T/0", "snoc_ddrt0_p1/T/0", "snoc_ddrt0_p2/T/0", "snoc_ddrt1_p1/T/0", "snoc_ddrt1_p2/T/0", "snoc_dspt/T/0", "snoc_lnoc/T/0", "snoc_mcput_d2d/T/0", "snoc_mnoc/T/0", "snoc_npu/T/0", "snoc_pciet/T/0", "snoc_rnoc/T/0", "snoc_service/T/0", "RESERVED1", "RESERVED2"; + }; + + TargetSubRange { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x09 0x06>; + }; + + SeqId { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x09>; + }; + }; + + ErrorLogger3 { + compatible = "eswin,eic7700,register"; + offset,length = <0x20 0x20>; + description = "Register 3 to log errors"; + aperture-link = <0x01>; + msb-link = <0x04>; + + AbsoluteAddress { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x09 0x0e>; + aperture-size = <0x49d>; + aperture-idx,aperture-base = <0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x52060000 0x00 0x00 0x00 0x01 0x00 0x01 0x00 0x72060000 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x52100000 0x00 0x00 0x00 0x01 0x00 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0x00 0x0b 0x00 0x79000000 0x00 0x01 0x00 0x08 0x00 0x0c 0x00 0x7a000000 0x00 0x01 0x00 0x08 0x00 0x0d 0x00 0x7b000000 0x00 0x01 0x00 0x08 0x00 0x0e 0x140 0x1000000 0x00 0x01 0x00 0x08 0x00 0x0f 0x140 0x2000000 0x00 0x01 0x00 0x08 0x00 0x10 0x140 0x3000000 0x00 0x01 0x00 0x08 0x00 0x11 0x140 0x9000000 0x00 0x01 0x00 0x08 0x00 0x12 0x140 0xa000000 0x00 0x01 0x00 0x08 0x00 0x13 0x140 0xb000000 0x00 0x01 0x00 0x08 0x00 0x14 0x00 0x50000000 0x00 0x01 0x00 0x08 0x00 0x15 0x00 0x70000000 0x00 0x01 0x00 0x08 0x00 0x16 0x00 0x40000000 0x00 0x01 0x00 0x08 0x00 0x17 0x00 0x60000000 0x00 0x01 0x00 0x08 0x00 0x18 0x00 0x80000000 0x00 0x01 0x00 0x08 0x00 0x19 0x01 0x00 0x00 0x01 0x00 0x08 0x00 0x1a 0x02 0x00 0x00 0x01 0x00 0x08 0x00 0x1b 0x04 0x00 0x00 0x01 0x00 0x08 0x00 0x1c 0x08 0x00 0x00 0x01 0x00 0x08 0x00 0x1d 0x18 0x00 0x00 0x01 0x00 0x08 0x00 0x1e 0x38 0x00 0x00 0x01 0x00 0x08 0x00 0x1f 0xd8 0x00 0x00 0x01 0x00 0x08 0x00 0x20 0xf8 0x00 0x00 0x01 0x00 0x08 0x00 0x21 0x20 0x00 0x00 0x01 0x00 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0x00 0x00 0x52080000 0x00 0x0e 0x00 0x0a 0x00 0x01 0x00 0x72080000 0x00 0x0e 0x00 0x0a 0x00 0x02 0x00 0x59000000 0x00 0x0e 0x00 0x0a 0x00 0x03 0x00 0x5a000000 0x00 0x0e 0x00 0x0a 0x00 0x04 0x00 0x79000000 0x00 0x0e 0x00 0x0a 0x00 0x05 0x00 0x7a000000 0x00 0x0e 0x00 0x0a 0x00 0x06 0x140 0x1000000 0x00 0x0e 0x00 0x0a 0x00 0x07 0x140 0x2000000 0x00 0x0e 0x00 0x0a 0x00 0x08 0x140 0x9000000 0x00 0x0e 0x00 0x0a 0x00 0x09 0x140 0xa000000 0x00 0x0e 0x00 0x0a 0x00 0x0a 0x18 0x00 0x00 0x0e 0x00 0x0a 0x00 0x0b 0x38 0x00 0x00 0x0e 0x00 0x0a 0x00 0x0c 0xd8 0x00 0x00 0x0e 0x00 0x0a 0x00 0x0d 0xf8 0x00 0x00 0x0e 0x00 0x0a 0x00 0x0e 0x70 0x00 0x00 0x0e 0x00 0x0a 0x00 0x0f 0x70 0x100 0x00 0x0e 0x00 0x0a 0x00 0x10 0x130 0x00 0x00 0x0e 0x00 0x0a 0x00 0x11 0x130 0x100 0x00 0x0e 0x00 0x0a 0x00 0x12 0x00 0x00 0x00 0x0e 0x00 0x0a 0x00 0x13 0x00 0x00>; + }; + }; + + ErrorLogger4 { + compatible = "eswin,eic7700,register"; + offset,length = <0x24 0x20>; + description = "Register 4 to log errors"; + + addr_msb { + compatible = "eswin,eic7700,bitfield"; + description = "Stores NTTP packet header field Addr (MSBs) of the logged error"; + offset,length = <0x00 0x09>; + }; + }; + + ErrorLogger5 { + compatible = "eswin,eic7700,register"; + offset,length = <0x28 0x20>; + description = "Register 5 to log errors"; + + User_flag { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x12>; + lut = "Cache_0", "Cache_1", "Cache_2", "Cache_3", "Prot_0 ", "Prot_1 ", "Prot_2 ", "User_0 ", "User_1 ", "User_2 ", "User_3 ", "User_4 ", "User_5 ", "User_6 ", "qos0", "qos1", "qos2", "qos3"; + }; + }; + }; + + d0_media_noc@52021400 { + compatible = "eswin,eic7700-noc"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + reg = <0x00 0x52021400 0x00 0x4000>; + interrupts = <0x1c6>; + interrupt-names = "error"; + interrupt-parent = <0x0f>; + errlogger,idx = <0x00 0x01 0x03 0x04 0x05>; + eswin,qos-configs = "GPU", "TBU2", "VC"; + eswin,GPU-qos-base = <0x52021480>; + eswin,GPU-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x1e0 0x14 0x01 0x18 0x01>; + eswin,TBU2-qos-base = <0x52021500>; + eswin,TBU2-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>; + eswin,VC-qos-base = <0x52021580>; + eswin,VC-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>; + status = "okay"; + stat,0 = "TracePort:ddr0_p3_req"; + stat,1 = "TracePort:ddr1_p3_req"; + + sideband_manager@52022000 { + compatible = "eswin,win2xxx-noc-sideband-manager"; + reg = <0x00 0x52022000 0x00 0x10>; + SenseIn0 = <0x46 0x00 0x47 0x01 0x48 0x02 0x49 0x03 0x4a 0x04>; + bf-name = "SBM_MNOC_GPU", "SBM_MNOC_TBU2", "SBM_MNOC_VC", "SBM_MNOC_DDRT0_P3", "SBM_MNOC_DDRT1_P3"; + }; + + mnoc_packet_ddr0_p3_req_probe@52020000 { + compatible = "eswin,win2xxx-noc-packet-probe"; + reg = <0x00 0x52020000 0x00 0x4000>; + clocks = <0x03 0x21a>; + clock-names = "clk"; + interrupts = <0x1ca>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x01>; + counter,nr = <0x02>; + portsel = "ddr0_p3_req"; + }; + + mnoc_packet_ddr1_p3_req_probe@52020800 { + compatible = "eswin,win2xxx-noc-packet-probe"; + reg = <0x00 0x52020800 0x00 0x4000>; + clocks = <0x03 0x21f>; + clock-names = "clk"; + interrupts = <0x1c8>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x01>; + counter,nr = <0x02>; + portsel = "ddr1_p3_req"; + }; + + mnoc_trans_probe@52021000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + compatible = "eswin,win2xxx-noc-trans-probe"; + reg = <0x00 0x52021000 0x00 0x4000>; + clocks = <0x03 0x203>; + clock-names = "clk"; + interrupts = <0x1c5>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x03>; + counter,nr = <0x0c>; + profiler,nr = <0x01>; + portsel = "gpu", "tbu2", "vc"; + + mnoc_trans_gpu_filter@52021600 { + status = "disabled"; + compatible = "eswin,win2xxx-noc-trans-filter"; + reg = <0x00 0x52021600 0x00 0x80>; + }; + + mnoc_trans_tbu2_filter@52021680 { + status = "disabled"; + compatible = "eswin,win2xxx-noc-trans-filter"; + reg = <0x00 0x52021680 0x00 0x80>; + }; + + mnoc_trans_vc_filter@52021700 { + status = "disabled"; + compatible = "eswin,win2xxx-noc-trans-filter"; + reg = <0x00 0x52021700 0x00 0x80>; + }; + + mnoc_trans_profiler@52021780 { + compatible = "eswin,win2xxx-noc-trans-profiler"; + reg = <0x00 0x52021780 0x00 0x80>; + }; + }; + + ErrorLogger0 { + compatible = "eswin,eic7700,register"; + offset,length = <0x14 0x20>; + description = "Register 0 to log errors"; + + lock { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x01>; + lut = "Not Locked", "Locked"; + }; + + OpCode { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x01 0x04>; + lut = "RD: data read with incrementing address", "RDW: data read with wrapping address", "RDL: allocates monitor in the Target with incrementing address", "RDX: exclusive read with incrementing address", "WR: data write with incrementing address", "WRW: data write with wrapping address", "WRC: conditional write if matching monitor in Target is found", "RSV: reserved", "PRE: preamble packet of linked sequence (locked sequence)", "URG: urgency packet used for QoS (status must be REQ)"; + }; + + ErrCode { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x08 0x03>; + lut = "SLV (error source: Target): error detected by the Slave without any information or no Error", "DEC (error source: Initiator NIU): decode error", "UNS (error source: Target NIU): unsupported access type", "DISC (error source: Power Disconnect): disconnected Target or NoC domain", "SEC (error source: Initiator NIU or Firewall): security error", "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator", "TMO (error source: Target NIU): time-out", "RSV: reserved"; + }; + + Len1 { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x10 0x0c>; + }; + + Format { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x1f 0x01>; + lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)"; + }; + }; + + ErrorLogger1 { + compatible = "eswin,eic7700,register", "eswin,eic7700,noc,filter,routeid"; + offset,length = <0x18 0x20>; + description = "Register 1 to log errors"; + + InitFlow { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x0e 0x02>; + lut = "gpu_mnoc/I/0", "snoc_mnoc/I/0", "tbu2_mnoc/I/0", "vc_mnoc/I/0"; + }; + + TargetFlow { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x0c 0x02>; + lut = "mnoc_ddrt0_p3/T/0", "mnoc_ddrt1_p3/T/0", "mnoc_service/T/0", "mnoc_snoc/T/0"; + }; + + TargetSubRange { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x09 0x03>; + }; + + SeqId { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x09>; + }; + }; + + ErrorLogger3 { + compatible = "eswin,eic7700,register"; + offset,length = <0x20 0x20>; + description = "Register 3 to log errors"; + aperture-link = <0x01>; + msb-link = <0x04>; + + AbsoluteAddress { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x09 0x07>; + aperture-size = <0x37>; + aperture-idx,aperture-base = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x40 0x100 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x00 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x00 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x00 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x00 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x00 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x00 0x00 0x01 0x00 0x06 0x40 0x80 0x00 0x00 0x00 0x01 0x00 0x07 0x40 0x180 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x00 0x00 0x52020000 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x72020000 0x00 0x01 0x00 0x02 0x00 0x02 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x03 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x02 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x02 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x02 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x02 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x02 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x02 0x00 0x00 0x00 0x06 0x40 0x00 0x00 0x02 0x00 0x00 0x00 0x07 0x40 0x100 0x00 0x02 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x02 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x02 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x02 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x02 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x02 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x02 0x00 0x01 0x00 0x06 0x40 0x80 0x00 0x02 0x00 0x01 0x00 0x07 0x40 0x180 0x00 0x02 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x03 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x03 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x03 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x03 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x03 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x03 0x00 0x00 0x00 0x06 0x40 0x00 0x00 0x03 0x00 0x00 0x00 0x07 0x40 0x100 0x00 0x03 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x03 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x03 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x03 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x03 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x03 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x03 0x00 0x01 0x00 0x06 0x40 0x80 0x00 0x03 0x00 0x01 0x00 0x07 0x40 0x180 0x00 0x03 0x00 0x03 0x00 0x00 0x00 0x00>; + }; + }; + + ErrorLogger4 { + compatible = "eswin,eic7700,register"; + offset,length = <0x24 0x20>; + description = "Register 4 to log errors"; + + addr_msb { + compatible = "eswin,eic7700,bitfield"; + description = "Stores NTTP packet header field Addr (MSBs) of the logged error"; + offset,length = <0x00 0x09>; + }; + }; + + ErrorLogger5 { + compatible = "eswin,eic7700,register"; + offset,length = <0x28 0x20>; + description = "Register 5 to log errors"; + + User_flag { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x12>; + lut = "Cache_0", "Cache_1", "Cache_2", "Cache_3", "Prot_0 ", "Prot_1 ", "Prot_2 ", "User_0 ", "User_1 ", "User_2 ", "User_3 ", "User_4 ", "User_5 ", "User_6 ", "qos0", "qos1", "qos2", "qos3"; + }; + }; + }; + + d0_realtime_noc@52041400 { + compatible = "eswin,eic7700-noc"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + reg = <0x00 0x52041400 0x00 0x4000>; + interrupts = <0x1c0>; + interrupt-names = "error"; + interrupt-parent = <0x0f>; + errlogger,idx = <0x00 0x01 0x03 0x04 0x05>; + eswin,qos-configs = "TBU0", "VO"; + eswin,TBU0-qos-base = <0x52041480>; + eswin,TBU0-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x1e0 0x14 0x01 0x18 0x01>; + eswin,VO-qos-base = <0x52041500>; + eswin,VO-qos-settings = <0x08 0x04 0x0c 0x02 0x10 0x18 0x14 0x10 0x18 0x01>; + status = "okay"; + stat,0 = "TracePort:ddr0_p4_req"; + stat,1 = "TracePort:ddr1_p4_req"; + + sideband_manager@52042000 { + compatible = "eswin,win2xxx-noc-sideband-manager"; + reg = <0x00 0x52042000 0x00 0x10>; + SenseIn0 = <0x50 0x00 0x51 0x01 0x52 0x02 0x53 0x03>; + bf-name = "SBM_RNOC_TBU0", "SBM_RNOC_VO", "SBM_RNOC_DDRT0_P4", "SBM_RNOC_DDRT1_P4"; + }; + + rnoc_packet_ddr0_p4_req_probe@52040000 { + compatible = "eswin,win2xxx-noc-packet-probe"; + reg = <0x00 0x52040000 0x00 0x4000>; + clocks = <0x03 0x21b>; + clock-names = "clk"; + interrupts = <0x1c4>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x01>; + counter,nr = <0x02>; + portsel = "ddr0_p4_req"; + }; + + rnoc_packet_ddr1_p4_req_probe@52040800 { + compatible = "eswin,win2xxx-noc-packet-probe"; + reg = <0x00 0x52040800 0x00 0x4000>; + clocks = <0x03 0x220>; + clock-names = "clk"; + interrupts = <0x1c2>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x01>; + counter,nr = <0x02>; + portsel = "ddr1_p4_req"; + }; + + rnoc_trans_probe@52041000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + compatible = "eswin,win2xxx-noc-trans-probe"; + reg = <0x00 0x52041000 0x00 0x4000>; + clocks = <0x03 0x203>; + clock-names = "clk"; + interrupts = <0x1bf>; + interrupt-names = "stat"; + interrupt-parent = <0x0f>; + filter,nr = <0x02>; + counter,nr = <0x08>; + profiler,nr = <0x01>; + portsel = "tbu0", "vo"; + + rnoc_trans_tbu0_filter@52041580 { + status = "disabled"; + compatible = "eswin,win2xxx-noc-trans-filter"; + reg = <0x00 0x52041580 0x00 0x80>; + }; + + rnoc_trans_vo_filter@52041600 { + status = "disabled"; + compatible = "eswin,win2xxx-noc-trans-filter"; + reg = <0x00 0x52041600 0x00 0x80>; + }; + + rnoc_trans_profiler@52041680 { + compatible = "eswin,win2xxx-noc-trans-profiler"; + reg = <0x00 0x52041680 0x00 0x80>; + }; + }; + + ErrorLogger0 { + compatible = "eswin,eic7700,register"; + offset,length = <0x14 0x20>; + description = "Register 0 to log errors"; + + lock { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x01>; + lut = "Not Locked", "Locked"; + }; + + OpCode { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x01 0x04>; + lut = "RD: data read with incrementing address", "RDW: data read with wrapping address", "RDL: allocates monitor in the Target with incrementing address", "RDX: exclusive read with incrementing address", "WR: data write with incrementing address", "WRW: data write with wrapping address", "WRC: conditional write if matching monitor in Target is found", "RSV: reserved", "PRE: preamble packet of linked sequence (locked sequence)", "URG: urgency packet used for QoS (status must be REQ)"; + }; + + ErrCode { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x08 0x03>; + lut = "SLV (error source: Target): error detected by the Slave without any information or no Error", "DEC (error source: Initiator NIU): decode error", "UNS (error source: Target NIU): unsupported access type", "DISC (error source: Power Disconnect): disconnected Target or NoC domain", "SEC (error source: Initiator NIU or Firewall): security error", "HIDE (error source: Firewall): hidden security error. Will be reported as OK to the initiator", "TMO (error source: Target NIU): time-out", "RSV: reserved"; + }; + + Len1 { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x10 0x0c>; + }; + + Format { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x1f 0x01>; + lut = "NTTP v3.0 (Invalid)", "NTTP v3.5 (Ok)"; + }; + }; + + ErrorLogger1 { + compatible = "eswin,eic7700,register", "eswin,eic7700,noc,filter,routeid"; + offset,length = <0x18 0x20>; + description = "Register 1 to log errors"; + + InitFlow { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x0e 0x02>; + lut = "snoc_rnoc/I/0", "tbu0_rnoc/I/0", "vo_rnoc/I/0", "RESERVED0"; + }; + + TargetFlow { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x0c 0x02>; + lut = "rnoc_ddrt0_p4/T/0", "rnoc_ddrt1_p4/T/0", "rnoc_service/T/0", "rnoc_snoc/T/0"; + }; + + TargetSubRange { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x09 0x03>; + }; + + SeqId { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x09>; + }; + }; + + ErrorLogger3 { + compatible = "eswin,eic7700,register"; + offset,length = <0x20 0x20>; + description = "Register 3 to log errors"; + aperture-link = <0x01>; + msb-link = <0x04>; + + AbsoluteAddress { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x09 0x07>; + aperture-size = <0x28>; + aperture-idx,aperture-base = <0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x52040000 0x00 0x00 0x00 0x02 0x00 0x01 0x00 0x72040000 0x00 0x00 0x00 0x02 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x03 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x01 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x01 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x01 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x01 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x01 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x01 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x01 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x01 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x01 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x01 0x00 0x03 0x00 0x00 0x00 0x59000000 0x00 0x01 0x00 0x03 0x00 0x01 0x00 0x79000000 0x00 0x01 0x00 0x03 0x00 0x02 0x140 0x1000000 0x00 0x01 0x00 0x03 0x00 0x03 0x140 0x9000000 0x00 0x01 0x00 0x03 0x00 0x04 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x80000000 0x00 0x02 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x02 0x00 0x00 0x00 0x02 0x02 0x00 0x00 0x02 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x02 0x00 0x00 0x00 0x04 0x08 0x00 0x00 0x02 0x00 0x00 0x00 0x05 0x20 0x00 0x00 0x02 0x00 0x01 0x00 0x00 0x00 0x80000080 0x00 0x02 0x00 0x01 0x00 0x01 0x01 0x80 0x00 0x02 0x00 0x01 0x00 0x02 0x02 0x80 0x00 0x02 0x00 0x01 0x00 0x03 0x04 0x80 0x00 0x02 0x00 0x01 0x00 0x04 0x08 0x80 0x00 0x02 0x00 0x01 0x00 0x05 0x20 0x80 0x00 0x02 0x00 0x03 0x00 0x00 0x00 0x59000000 0x00 0x02 0x00 0x03 0x00 0x01 0x00 0x79000000 0x00 0x02 0x00 0x03 0x00 0x02 0x140 0x1000000 0x00 0x02 0x00 0x03 0x00 0x03 0x140 0x9000000 0x00 0x02 0x00 0x03 0x00 0x04 0x00 0x00 0x00 0x02 0x00 0x03 0x00 0x05 0x00 0x00>; + }; + }; + + ErrorLogger4 { + compatible = "eswin,eic7700,register"; + offset,length = <0x24 0x20>; + description = "Register 4 to log errors"; + + addr_msb { + compatible = "eswin,eic7700,bitfield"; + description = "Stores NTTP packet header field Addr (MSBs) of the logged error"; + offset,length = <0x00 0x09>; + }; + }; + + ErrorLogger5 { + compatible = "eswin,eic7700,register"; + offset,length = <0x28 0x20>; + description = "Register 5 to log errors"; + + User_flag { + compatible = "eswin,eic7700,bitfield"; + offset,length = <0x00 0x10>; + lut = "Cache_0", "Cache_1", "Cache_2", "Cache_3", "Prot_0 ", "Prot_1 ", "Prot_2 ", "User_0 ", "User_1 ", "User_2 ", "User_3 ", "User_4 ", "qos0", "qos1", "qos2", "qos3"; + }; + }; + }; + }; + + eswin-npu@51c00000 { + compatible = "eswin,npu0"; + reg = <0x00 0x51c00000 0x00 0x400000>; + interrupt-parent = <0x0f>; + interrupts = <0x183 0x10>; + #size-cells = <0x02>; + dma-ranges = <0x01 0x00 0x00 0xc0000000 0x1ff 0x00>; + iommus = <0x18 0x04>; + tbus = <0x05>; + dsp-avail-num = <0x01>; + spram-size = <0x400000>; + npu_mbox = <0x20>; + resets = <0x17 0x06 0x08>; + reset-names = "e31_core"; + numa-node-id = <0x00>; + status = "okay"; + }; + + llc@51c00000 { + compatible = "eswin,llc"; + reg = <0x00 0x51c00000 0x00 0x400000>; + eswin,syscfg = <0x16 0x324>; + eswin,syscrg_csr = <0x15>; + clocks = <0x03 0x236 0x03 0x237 0x03 0x23a 0x03 0x23c 0x03 0x26 0x03 0x0b>; + clock-names = "aclk", "cfg_clk", "llc_clk", "core_clk", "mux_u_npu_core_3mux1_gfree", "fixed_rate_clk_spll2_fout2", "fixed_rate_clk_spll1_fout1"; + resets = <0x17 0x06 0x01 0x17 0x06 0x02 0x17 0x06 0x04 0x17 0x06 0x40>; + reset-names = "axi", "cfg", "core", "llc"; + numa-node-id = <0x00>; + spram-region = <0x21>; + }; + + dsp_subsys@52280400 { + #address-cells = <0x02>; + #size-cells = <0x02>; + reg = <0x00 0x52280400 0x00 0x10000 0x00 0x51810000 0x00 0x8000>; + ranges; + compatible = "es-dsp-subsys", "simple-bus"; + clocks = <0x03 0x210>; + clock-names = "cfg_clk"; + resets = <0x17 0x02 0x01 0x17 0x02 0x02 0x17 0x02 0x04 0x17 0x02 0x10 0x17 0x02 0x20 0x17 0x02 0x40 0x17 0x02 0x80>; + reset-names = "axi", "cfg", "div4", "div_0", "div_1", "div_2", "div_3"; + status = "okay"; + + es_dsp@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "eswin-dsp", "cdns,xrp-hw-eswin"; + ranges = <0x28000000 0x00 0x5b000000 0x8000 0x28100000 0x00 0x5b100000 0x20000 0x28120000 0x00 0x5b120000 0x20000>; + clocks = <0x03 0x2a8>; + clock-names = "aclk"; + dsp_mbox = <0x22>; + device-irq = <0x0b 0x50a90000 0x20 0x50a80000 0x01 0x50a40000>; + device-uart = <0x50900000>; + device-irq-mode = <0x01>; + host-irq-mode = <0x01>; + firmware-name = "eic7700_dsp_fw"; + process-id = <0x00>; + dma-ranges = <0x30000000 0x00 0xc0000000 0xce000000>; + iommus = <0x18 0x12>; + tbus = <0x70>; + numa-node-id = <0x00>; + aux-e31-dtim = <0x5a110000>; + status = "okay"; + + dsp@0 { + }; + }; + + es_dsp@1 { + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "eswin-dsp", "cdns,xrp-hw-eswin"; + ranges = <0x28000000 0x00 0x5b008000 0x8000 0x28100000 0x00 0x5b140000 0x20000 0x28120000 0x00 0x5b160000 0x20000>; + clocks = <0x03 0x2a9>; + clock-names = "aclk"; + dsp_mbox = <0x23>; + device-irq = <0x0d 0x50ab0000 0x40 0x50aa0000 0x01 0x50a40000>; + device-uart = <0x50900000>; + device-irq-mode = <0x01>; + host-irq-mode = <0x01>; + firmware-name = "eic7700_dsp_fw"; + process-id = <0x01>; + dma-ranges = <0x30000000 0x00 0xc0000000 0xce000000>; + iommus = <0x18 0x13>; + tbus = <0x71>; + numa-node-id = <0x00>; + aux-e31-dtim = <0x5a110000>; + status = "okay"; + + dsp@0 { + }; + }; + + es_dsp@2 { + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "eswin-dsp", "cdns,xrp-hw-eswin"; + ranges = <0x28000000 0x00 0x5b010000 0x8000 0x28100000 0x00 0x5b180000 0x20000 0x28120000 0x00 0x5b1a0000 0x20000>; + clocks = <0x03 0x2aa>; + clock-names = "aclk"; + dsp_mbox = <0x24>; + device-irq = <0x0f 0x50ad0000 0x80 0x50ac0000 0x01 0x50a40000>; + device-uart = <0x50900000>; + device-irq-mode = <0x01>; + host-irq-mode = <0x01>; + firmware-name = "eic7700_dsp_fw"; + process-id = <0x02>; + dma-ranges = <0x30000000 0x00 0xc0000000 0xce000000>; + iommus = <0x18 0x14>; + tbus = <0x72>; + numa-node-id = <0x00>; + aux-e31-dtim = <0x5a110000>; + status = "okay"; + + dsp@0 { + }; + }; + + es_dsp@3 { + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "eswin-dsp", "cdns,xrp-hw-eswin"; + ranges = <0x28000000 0x00 0x5b018000 0x8000 0x28100000 0x00 0x5b1c0000 0x20000 0x28120000 0x00 0x5b1e0000 0x20000>; + clocks = <0x03 0x2ab>; + clock-names = "aclk"; + dsp_mbox = <0x25>; + device-irq = <0x11 0x50af0000 0x100 0x50ae0000 0x01 0x50a40000>; + device-uart = <0x50900000>; + device-irq-mode = <0x01>; + host-irq-mode = <0x01>; + firmware-name = "eic7700_dsp_fw"; + process-id = <0x03>; + dma-ranges = <0x30000000 0x00 0xc0000000 0xce000000>; + iommus = <0x18 0x15>; + tbus = <0x73>; + numa-node-id = <0x00>; + aux-e31-dtim = <0x5a110000>; + status = "okay"; + + dsp@0 { + }; + }; + }; + + g2d@50140000 { + compatible = "eswin,galcore_d0"; + clocks = <0x03 0x254 0x03 0x255 0x03 0x25a 0x03 0x25b 0x03 0x25c 0x03 0x25d 0x03 0x2b1>; + clock-names = "vc_aclk", "vc_cfg", "g2d_cfg", "g2d_st2", "g2d_clk", "g2d_aclk", "mon_pclk"; + resets = <0x17 0x16 0x02 0x17 0x16 0x01 0x17 0x16 0x04 0x17 0x1b 0x01 0x17 0x1b 0x02 0x17 0x1b 0x04>; + reset-names = "axi", "cfg", "moncfg", "g2d_core", "g2d_cfg", "g2d_axi"; + reg = <0x00 0x50140000 0x00 0x40000 0x00 0x50180000 0x00 0x40000>; + reg-names = "core_2d", "core_2d1"; + fe-apb-offset = <0x800>; + interrupt-parent = <0x0f>; + interrupts = <0x31 0x32>; + interrupt-names = "core_2d", "core_2d1"; + enable-mmu = <0x01>; + contiguous-size = <0xa00000>; + recovery = <0x00>; + status = "okay"; + }; + + gpu@51400000 { + compatible = "img,gpu"; + #address-cells = <0x02>; + #size-cells = <0x02>; + reg = <0x00 0x51400000 0x00 0xfffff>; + clocks = <0x03 0x20b 0x03 0x20c 0x03 0x20d>; + clock-names = "aclk", "gray_clk", "cfg_clk"; + resets = <0x17 0x01 0x01 0x17 0x01 0x02 0x17 0x01 0x04 0x17 0x01 0x08 0x17 0x01 0x10>; + reset-names = "axi", "cfg", "gray", "jones", "spu"; + interrupt-parent = <0x0f>; + interrupts = <0x0f>; + status = "okay"; + }; + + sata@0x50420000 { + compatible = "snps,eswin-ahci"; + reg = <0x00 0x50420000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupt-names = "intrq", "msi", "pme"; + interrupts = <0x3a 0x3b 0x3c>; + ports-implemented = <0x01>; + resets = <0x17 0x07 0x200 0x17 0x07 0x400 0x17 0x07 0x800 0x17 0x07 0x1000 0x17 0x07 0x8000000>; + reset-names = "asic0", "oob", "pmalive", "rbc", "apb"; + #size-cells = <0x02>; + iommus = <0x18 0x0e>; + tbus = <0x02>; + dma-ranges = <0x00 0x00 0x00 0xc0000000 0x200 0x00>; + eswin,hsp_sp_csr = <0x19 0x1050>; + eswin,syscrg_csr = <0x15 0x41c>; + numa-node-id = <0x00>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x26>; + }; + + pcie@0x54000000 { + compatible = "eswin,eic7700-pcie"; + clocks = <0x03 0x232 0x03 0x233 0x03 0x234 0x03 0x235>; + clock-names = "pcie_aclk", "pcie_cfg_clk", "pcie_cr_clk", "pcie_aux_clk"; + reset-names = "pcie_cfg", "pcie_powerup", "pcie_pwren"; + resets = <0x17 0x08 0x01 0x17 0x08 0x02 0x17 0x08 0x04>; + #address-cells = <0x03>; + #size-cells = <0x02>; + #interrupt-cells = <0x01>; + reg = <0x00 0x54000000 0x00 0x4000000 0x00 0x40000000 0x00 0x800000 0x00 0x50000000 0x00 0x100000>; + reg-names = "dbi", "config", "mgmt"; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x40800000 0x00 0x40800000 0x00 0x800000 0x82000000 0x00 0x41000000 0x00 0x41000000 0x00 0xf000000 0xc3000000 0x80 0x00 0x80 0x00 0x02 0x00>; + interrupts = <0xdc>; + interrupt-names = "msi"; + interrupt-parent = <0x0f>; + iommus = <0x18 0xfe0000>; + iommu-map = <0x00 0x18 0xff0000 0xffffff>; + gen-x = <0x03>; + lane-x = <0x04>; + tbus = <0x03>; + status = "okay"; + numa-node-id = <0x00>; + }; + + spi@50810000 { + compatible = "snps,eic7700-spi"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x50810000 0x00 0x4000>; + spi-max-frequency = "", "I>"; + clocks = <0x03 0x29c>; + clock-names = "clk"; + interrupt-parent = <0x0f>; + interrupts = <0x5b>; + resets = <0x17 0x10 0x01>; + reset-names = "spi"; + eswin,spi_dma = <0x27>; + dmas = <0x27 0x26 0x03 0x27 0x27 0x03>; + dma-names = "rx", "tx"; + numa-node-id = <0x00>; + status = "disabled"; + }; + + spi@50814000 { + compatible = "snps,eic7700-spi"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x50814000 0x00 0x4000>; + spi-max-frequency = "", "I>"; + clocks = <0x03 0x29d>; + clock-names = "clk"; + interrupt-parent = <0x0f>; + interrupts = <0x5c>; + resets = <0x17 0x10 0x02>; + reset-names = "spi"; + eswin,spi_dma = <0x27>; + dmas = <0x27 0x24 0x04 0x27 0x25 0x04>; + dma-names = "rx", "tx"; + numa-node-id = <0x00>; + status = "disabled"; + }; + + spi@51800000 { + compatible = "eswin,bootspi"; + reg = <0x00 0x51800000 0x00 0x8000 0x00 0x51828000 0x00 0x8000 0x00 0x5c000000 0x00 0x8000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x03 0x205 0x03 0x204>; + clock-names = "cfg_clk", "clk"; + resets = <0x17 0x24 0x02>; + reset-names = "rst"; + spi-max-frequency = "", "I>"; + reg-io-width = <0x04>; + status = "okay"; + num-cs = <0x01>; + cs-gpios = <0x1c 0x00 0x01>; + + spi-flash@0 { + compatible = "winbond,w25q128jw", "jedec,spi-nor"; + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x01>; + spi-max-frequency = "", "I>"; + rx-sample-delay-ns = <0x0a>; + }; + }; + + mmc@50450000 { + compatible = "eswin,emmc-sdhci-5.1"; + reg = <0x00 0x50450000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0x4f>; + assigned-clocks = <0x03 0x22a>; + assigned-clock-rates = <0xbebc200>; + clocks = <0x03 0x22a 0x03 0x222>; + clock-names = "clk_xin", "clk_ahb"; + clock-output-names = "emmc_cardclock"; + #clock-cells = <0x00>; + resets = <0x17 0x07 0x40 0x17 0x07 0x08 0x17 0x07 0x80000 0x17 0x07 0x800000>; + reset-names = "txrx_rst", "phy_rst", "prstn", "arstn"; + disable-cqe-dcmd; + bus-width = <0x08>; + non-removable; + mmc-hs400-1_8v; + max-frequency = <0xbebc200>; + #size-cells = <0x02>; + iommus = <0x18 0x0f>; + tbus = <0x02>; + dma-ranges = <0x00 0x00 0x00 0xc0000000 0x01 0x00>; + eswin,hsp_sp_csr = <0x19 0x1038>; + status = "okay"; + numa-node-id = <0x00>; + delay_code = <0x17>; + drive-impedance-ohm = <0x32>; + enable-cmd-pullup; + enable-data-pullup; + pinctrl-names = "default"; + pinctrl-0 = <0x28>; + }; + + mmc@0x50460000 { + compatible = "eswin,sdhci-sdio"; + reg = <0x00 0x50460000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0x51>; + clocks = <0x03 0x22b 0x03 0x222 0x03 0x0c 0x03 0x23>; + clock-names = "clk_xin", "clk_ahb", "clk_spll2_fout3", "clk_mux1_1"; + clock-output-names = "sdio0_cardclock"; + #clock-cells = <0x00>; + resets = <0x17 0x07 0x80 0x17 0x07 0x10 0x17 0x07 0x40000 0x17 0x07 0x400000>; + reset-names = "txrx_rst", "phy_rst", "prstn", "arstn"; + core-clk-reg = <0x51828164>; + clock-frequency = <0xc65d400>; + max-frequency = <0xc65d400>; + #size-cells = <0x02>; + dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>; + iommus = <0x18 0x10>; + tbus = <0x02>; + eswin,hsp_sp_csr = <0x19 0x103c>; + bus-width = <0x04>; + sdio-id = <0x00>; + numa-node-id = <0x00>; + status = "okay"; + delay_code = <0x29>; + drive-impedance-ohm = <0x21>; + enable-cmd-pullup; + enable-data-pullup; + no-sdio; + no-mmc; + }; + + mmc@0x50470000 { + compatible = "eswin,sdhci-sdio"; + reg = <0x00 0x50470000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0x53>; + clocks = <0x03 0x22c 0x03 0x222 0x03 0x0c 0x03 0x23>; + clock-names = "clk_xin", "clk_ahb", "clk_spll2_fout3", "clk_mux1_1"; + clock-output-names = "sdio1_cardclock"; + #clock-cells = <0x00>; + resets = <0x17 0x07 0x100 0x17 0x07 0x20 0x17 0x07 0x20000 0x17 0x07 0x200000>; + reset-names = "txrx_rst", "phy_rst", "prstn", "arstn"; + core-clk-reg = <0x51828168>; + clock-frequency = <0xc65d400>; + max-frequency = <0xc65d400>; + #size-cells = <0x02>; + dma-ranges = <0x00 0x20000000 0x00 0xc0000000 0x00 0x40000000>; + iommus = <0x18 0x11>; + tbus = <0x02>; + eswin,hsp_sp_csr = <0x19 0x1040>; + bus-width = <0x04>; + sdio-id = <0x01>; + numa-node-id = <0x00>; + status = "okay"; + delay_code = <0x29>; + drive-impedance-ohm = <0x21>; + enable-cmd-pullup; + enable-data-pullup; + non-removable; + no-sd; + no-mmc; + }; + + video-decoder0@50100000 { + compatible = "eswin,video-decoder0"; + clocks = <0x03 0x254 0x03 0x255 0x03 0x257 0x03 0x259 0x03 0x2e 0x03 0x04 0x03 0x0a 0x03 0x2ae 0x03 0x2b0 0x03 0x2b1>; + clock-names = "aclk", "cfg_clk", "jd_clk", "vd_clk", "vc_mux", "spll0_fout1", "spll2_fout1", "jd_pclk", "vd_pclk", "mon_pclk"; + resets = <0x17 0x16 0x02 0x17 0x16 0x01 0x17 0x16 0x04 0x17 0x17 0x01 0x17 0x17 0x02 0x17 0x19 0x01 0x17 0x19 0x02>; + reset-names = "axi", "cfg", "moncfg", "jd_cfg", "jd_axi", "vd_cfg", "vd_axi"; + eswin,syscfg = <0x16 0x00 0x04>; + vcmd-core = <0x00 0x6c>; + axife-core = <0x200 0x100>; + vdec-core = <0x800 0xc00>; + interrupt-parent = <0x0f>; + #size-cells = <0x02>; + dma-ranges = <0x00 0x00 0x00 0x80000000 0x200 0x00>; + vccsr-reg = <0x00 0x501c0000 0x00 0x1000>; + numa-node-id = <0x00>; + tbus = <0x10 0x13>; + status = "okay"; + + vdec0@50100000 { + core-name = "video-dec0"; + base-addr = <0x50100000>; + interrupts = <0xec>; + }; + + jdec0@50120000 { + core-name = "jpeg-dec0"; + base-addr = <0x50120000>; + interrupts = <0xed>; + }; + }; + + video-encoder@50110000 { + compatible = "eswin,video-encoder0"; + clocks = <0x03 0x254 0x03 0x255 0x03 0x256 0x03 0x258 0x03 0x2e 0x03 0x04 0x03 0x0a 0x03 0x2ad 0x03 0x2af 0x03 0x2b1>; + clock-names = "aclk", "cfg_clk", "je_clk", "ve_clk", "vc_mux", "spll0_fout1", "spll2_fout1", "je_pclk", "ve_pclk", "mon_pclk"; + resets = <0x17 0x16 0x02 0x17 0x16 0x01 0x17 0x16 0x04 0x17 0x18 0x01 0x17 0x18 0x02 0x17 0x1a 0x02 0x17 0x1a 0x01>; + reset-names = "axi", "cfg", "moncfg", "je_cfg", "je_axi", "ve_cfg", "ve_axi"; + eswin,syscfg = <0x16 0x00 0x04>; + vcmd-core = <0x00 0x6c>; + axife-core = <0x2000 0x7d0>; + venc-core = <0x1000 0x87c>; + interrupt-parent = <0x0f>; + #size-cells = <0x02>; + dma-ranges = <0x00 0x00 0x00 0x80000000 0x200 0x00>; + vccsr-reg = <0x00 0x501c0000 0x00 0x1000>; + numa-node-id = <0x00>; + tbus = <0x11 0x12>; + status = "okay"; + + venc0@50110000 { + core-name = "video-enc0"; + base-addr = <0x50110000>; + interrupts = <0xe5>; + }; + + jenc0@50130000 { + core-name = "jpeg-enc0"; + base-addr = <0x50130000>; + interrupts = <0xe8>; + }; + }; + + mbox@50a00000 { + compatible = "eswin,eic7700-mailbox"; + reg = <0x00 0x50a00000 0x00 0x10000 0x00 0x50a10000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0x75>; + #mbox-cells = <0x01>; + clocks = <0x03 0x27e 0x03 0x27f>; + clock-names = "pclk_mailbox_host", "pclk_mailbox_device"; + resets = <0x17 0x0c 0x01 0x17 0x0c 0x02>; + reset-names = "rst", "rst_device"; + lock-bit = <0x01>; + irq-bit = <0x02>; + status = "okay"; + phandle = <0x29>; + }; + + mbox@50a20000 { + compatible = "eswin,eic7700-mailbox"; + reg = <0x00 0x50a20000 0x00 0x10000 0x00 0x50a30000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0x77>; + #mbox-cells = <0x01>; + clocks = <0x03 0x280 0x03 0x281>; + clock-names = "pclk_mailbox_host", "pclk_mailbox_device"; + resets = <0x17 0x0c 0x04 0x17 0x0c 0x08>; + reset-names = "rst", "rst_device"; + lock-bit = <0x01>; + irq-bit = <0x04>; + status = "okay"; + phandle = <0x2b>; + }; + + mbox@50a40000 { + compatible = "eswin,npu0-mailbox"; + reg = <0x00 0x50a40000 0x00 0x10000 0x00 0x50a50000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0x79>; + #mbox-cells = <0x01>; + clocks = <0x03 0x282 0x03 0x283>; + clock-names = "pclk_mailbox_host", "pclk_mailbox_device"; + resets = <0x17 0x0c 0x10 0x17 0x0c 0x20>; + reset-names = "rst", "rst_device"; + lock-bit = <0x01>; + irq-bit = <0x08>; + status = "okay"; + phandle = <0x20>; + }; + + mbox@50a60000 { + compatible = "eswin,eic7700-mailbox"; + reg = <0x00 0x50a60000 0x00 0x10000 0x00 0x50a70000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0x7b>; + #mbox-cells = <0x01>; + clocks = <0x03 0x284 0x03 0x285>; + clock-names = "pclk_mailbox_host", "pclk_mailbox_device"; + resets = <0x17 0x0c 0x40 0x17 0x0c 0x80>; + reset-names = "rst", "rst_device"; + lock-bit = <0x01>; + irq-bit = <0x10>; + status = "okay"; + }; + + mbox@50a80000 { + compatible = "eswin,dsp0-mailbox"; + reg = <0x00 0x50a80000 0x00 0x10000 0x00 0x50a90000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0x7d>; + #mbox-cells = <0x01>; + clocks = <0x03 0x286 0x03 0x287>; + clock-names = "pclk_mailbox_host", "pclk_mailbox_device"; + resets = <0x17 0x0c 0x100 0x17 0x0c 0x200>; + reset-names = "rst", "rst_device"; + lock-bit = <0x01>; + irq-bit = <0x20>; + status = "okay"; + phandle = <0x22>; + }; + + mbox@50aa0000 { + compatible = "eswin,dsp1-mailbox"; + reg = <0x00 0x50aa0000 0x00 0x10000 0x00 0x50ab0000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0x7f>; + #mbox-cells = <0x01>; + clocks = <0x03 0x288 0x03 0x289>; + clock-names = "pclk_mailbox_host", "pclk_mailbox_device"; + resets = <0x17 0x0c 0x400 0x17 0x0c 0x800>; + reset-names = "rst", "rst_device"; + lock-bit = <0x01>; + irq-bit = <0x40>; + status = "okay"; + phandle = <0x23>; + }; + + mbox@50ac0000 { + compatible = "eswin,dsp2-mailbox"; + reg = <0x00 0x50ac0000 0x00 0x10000 0x00 0x50ad0000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0x81>; + #mbox-cells = <0x01>; + clocks = <0x03 0x28a 0x03 0x28b>; + clock-names = "pclk_mailbox_host", "pclk_mailbox_device"; + resets = <0x17 0x0c 0x1000 0x17 0x0c 0x2000>; + reset-names = "rst", "rst_device"; + lock-bit = <0x01>; + irq-bit = <0x80>; + status = "okay"; + phandle = <0x24>; + }; + + mbox@50ae0000 { + compatible = "eswin,dsp3-mailbox"; + reg = <0x00 0x50ae0000 0x00 0x10000 0x00 0x50af0000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0x83>; + #mbox-cells = <0x01>; + clocks = <0x03 0x28c 0x03 0x28d>; + clock-names = "pclk_mailbox_host", "pclk_mailbox_device"; + resets = <0x17 0x0c 0x4000 0x17 0x0c 0x8000>; + reset-names = "rst", "rst_device"; + lock-bit = <0x01>; + irq-bit = <0x100>; + status = "okay"; + phandle = <0x25>; + }; + + ipc@0 { + compatible = "eswin,eic7700-ipc"; + #size-cells = <0x02>; + dma-ranges = <0x00 0x80000000 0x00 0xc0000000 0x00 0x80000000>; + iommus = <0x18 0x18>; + tbus = <0x04>; + eswin,syscfg = <0x16 0x1004 0x00 0x16 0x4004 0x00>; + mboxes = <0x29 0x00>; + mbox-names = "u84_scpu"; + numa-node-id = <0x00>; + status = "okay"; + }; + + lpcpu@0 { + compatible = "eswin,eic7700-lpcpu"; + fw-region = <0x2a>; + clocks = <0x03 0x209 0x03 0x20a>; + clock-names = "core_clk", "bus_clk"; + reset-names = "core_rst", "bus_rst", "dbg_rst"; + resets = <0x17 0x15 0x01 0x17 0x15 0x02 0x17 0x15 0x04>; + #size-cells = <0x02>; + dma-ranges = <0x00 0xb0000000 0x00 0xc0000000 0x00 0x50000000>; + iommus = <0x18 0x19>; + eswin,syscfg = <0x16 0x2004 0x00>; + tbus = <0x04>; + mboxes = <0x2b 0x00>; + mbox-names = "u84_lpcpu"; + numa-node-id = <0x00>; + status = "disabled"; + }; + + pvt@0x50b00000 { + compatible = "eswin,eswin-pvt"; + clocks = <0x03 0x25f>; + clock-names = "pvt_clk"; + resets = <0x17 0x0b 0x01>; + reset-names = "pvt_rst"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x50b00000 0x00 0x10000>; + interrupts = <0x15d>; + interrupt-parent = <0x0f>; + status = "okay"; + }; + + pvt@0x52360000 { + compatible = "eswin,eswin-pvt"; + clocks = <0x03 0x260>; + clock-names = "pvt_clk"; + resets = <0x17 0x0b 0x02>; + reset-names = "pvt_rst"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x52360000 0x00 0x20000>; + interrupts = <0x15e>; + interrupt-parent = <0x0f>; + status = "okay"; + }; + + fan_control@50b50000 { + compatible = "eswin-fan-control"; + reg = <0x00 0x50b50000 0x00 0x10000>; + clocks = <0x03 0x2a7>; + clock-names = "pclk"; + resets = <0x17 0x0a 0x01>; + reset-names = "fan_rst"; + interrupt-parent = <0x0f>; + interrupt-names = "fanirq"; + interrupts = <0x162>; + pulses-per-revolution = <0x02>; + pwm-minimum-period = <0x3e8>; + pwms = <0x2c 0x00 0x186a0>; + pinctrl-names = "default"; + pinctrl-0 = <0x2d>; + status = "okay"; + }; + + i2c@50950000 { + compatible = "snps,designware-i2c"; + clock-frequency = <0x186a0>; + clocks = <0x03 0x28e>; + clock-names = "pclk"; + resets = <0x17 0x09 0x01>; + reset-names = "rst"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x50950000 0x00 0x8000>; + interrupts = <0x69>; + interrupt-parent = <0x0f>; + status = "okay"; + + es8388-0@11 { + compatible = "eswin,es8388"; + reg = <0x11>; + #sound-dai-cells = <0x00>; + eswin-plat = <0x02>; + pinctrl-names = "default"; + pinctrl-0 = <0x2e 0x2f>; + front-jack-gpios = <0x30 0x00 0x00>; + back-jack-gpios = <0x30 0x1c 0x00>; + + port { + + endpoint { + system-clock-frequency = <0xbb8000>; + remote-endpoint = <0x31>; + phandle = <0x50>; + }; + }; + }; + }; + + i2c@50960000 { + compatible = "snps,designware-i2c"; + clock-frequency = <0x186a0>; + clocks = <0x03 0x28f>; + clock-names = "pclk"; + resets = <0x17 0x09 0x02>; + reset-names = "rst"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x50960000 0x00 0x10000>; + interrupts = <0x6a>; + interrupt-parent = <0x0f>; + status = "disabled"; + }; + + i2c@50970000 { + compatible = "snps,designware-i2c"; + clock-frequency = <0x186a0>; + clocks = <0x03 0x290>; + clock-names = "pclk"; + resets = <0x17 0x09 0x04>; + reset-names = "rst"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x50970000 0x00 0x8000>; + interrupts = <0x6b>; + interrupt-parent = <0x0f>; + status = "disabled"; + }; + + i2c@50980000 { + compatible = "snps,designware-i2c"; + clock-frequency = <0x186a0>; + clocks = <0x03 0x291>; + clock-names = "pclk"; + resets = <0x17 0x09 0x08>; + reset-names = "rst"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x50980000 0x00 0x8000>; + interrupts = <0x6c>; + interrupt-parent = <0x0f>; + status = "okay"; + + fusb303b@21 { + compatible = "fcs,fusb303b"; + status = "okay"; + reg = <0x21>; + eswin,syscfg = <0x16 0x3c0 0x0c>; + pinctrl-names = "default"; + pinctrl-0 = <0x32>; + int-gpios = <0x30 0x05 0x00>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "host"; + }; + }; + }; + + i2c@50990000 { + compatible = "snps,designware-i2c"; + clock-frequency = <0x186a0>; + clocks = <0x03 0x292>; + clock-names = "pclk"; + resets = <0x17 0x09 0x10>; + reset-names = "rst"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x50990000 0x00 0x8000>; + interrupts = <0x6d>; + interrupt-parent = <0x0f>; + status = "disabled"; + }; + + i2c@509a0000 { + compatible = "snps,designware-i2c"; + clock-frequency = <0x186a0>; + clocks = <0x03 0x293>; + clock-names = "pclk"; + resets = <0x17 0x09 0x20>; + reset-names = "rst"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x509a0000 0x00 0x8000>; + interrupts = <0x6e>; + interrupt-parent = <0x0f>; + status = "okay"; + }; + + i2c@509b0000 { + compatible = "snps,designware-i2c"; + clock-frequency = <0x186a0>; + clocks = <0x03 0x294>; + clock-names = "pclk"; + resets = <0x17 0x09 0x40>; + reset-names = "rst"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x509b0000 0x00 0x8000>; + interrupts = <0x6f>; + interrupt-parent = <0x0f>; + status = "disabled"; + }; + + i2c@509c0000 { + compatible = "snps,designware-i2c"; + clock-frequency = <0x186a0>; + clocks = <0x03 0x295>; + clock-names = "pclk"; + resets = <0x17 0x09 0x80>; + reset-names = "rst"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x509c0000 0x00 0x8000>; + interrupts = <0x70>; + interrupt-parent = <0x0f>; + status = "disabled"; + }; + + i2c@509d0000 { + compatible = "snps,designware-i2c"; + clock-frequency = <0x186a0>; + clocks = <0x03 0x296>; + clock-names = "pclk"; + resets = <0x17 0x09 0x100>; + reset-names = "rst"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x509d0000 0x00 0x8000>; + interrupts = <0x71>; + interrupt-parent = <0x0f>; + status = "disabled"; + }; + + i2c@509e0000 { + compatible = "snps,designware-i2c"; + clock-frequency = <0x186a0>; + clocks = <0x03 0x297>; + clock-names = "pclk"; + resets = <0x17 0x09 0x200>; + reset-names = "rst"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x509e0000 0x00 0x8000>; + interrupts = <0x72>; + interrupt-parent = <0x0f>; + status = "disabled"; + }; + + i2c@51830000 { + compatible = "snps,designware-i2c"; + clock-frequency = <0x186a0>; + clocks = <0x03 0x29f>; + clock-names = "pclk"; + resets = <0x17 0x26 0x01>; + reset-names = "rst"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x51830000 0x00 0x8000>; + interrupts = <0x122>; + interrupt-parent = <0x0f>; + eswin,i2c_dma = <0x27>; + dma-names = "rx", "tx"; + dmas = <0x27 0x29 0xff 0x27 0x2a 0xff>; + status = "okay"; + eswin,syscfg = <0x16 0x3c0 0x10>; + + aon_eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + + i2c@51838000 { + compatible = "snps,designware-i2c"; + clock-frequency = <0x186a0>; + clocks = <0x03 0x2a0>; + clock-names = "pclk"; + resets = <0x17 0x25 0x01>; + reset-names = "rst"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0x51838000 0x00 0x8000>; + interrupts = <0x123>; + interrupt-parent = <0x0f>; + status = "okay"; + eswin,syscfg = <0x16 0x3c0 0x0f>; + iic_hold_time = <0x40>; + + pac1934@10 { + compatible = "microchip,pac1934"; + update_time_ms = <0x3e8>; + eswin,chan_label = "som vdd", "soc vdd", "cpu vdd", "ddr lpvdd"; + label = "som_info"; + energy_acc_count = <0x00>; + shunt_resistors = <0x01 0x01 0x01 0x01>; + reg = <0x10>; + }; + + ina226@44 { + compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "sys_power"; + reg = <0x44>; + shunt-resistor = <0x3e8>; + }; + }; + + pinctrl@0x51600080 { + compatible = "eswin,eic7700-pinctrl", "syscon"; + reg = <0x00 0x51600080 0x00 0x1fff80>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d>; + phandle = <0x1d>; + + sdio0-default { + + mux { + groups = "sdio0_group"; + function = "sdio0_func"; + }; + }; + + sdio1-default { + + mux { + groups = "sdio1_group"; + function = "sdio1_func"; + }; + }; + + por_sel-default { + + mux { + groups = "por_sel_group"; + function = "por_sel_func"; + }; + }; + + jtag0-default { + + mux { + groups = "jtag0_group"; + function = "jtag0_func"; + }; + }; + + jtag1-default { + + mux { + groups = "jtag1_group"; + function = "jtag1_func"; + }; + }; + + jtag2-default { + + mux { + groups = "jtag2_group"; + function = "jtag2_func"; + }; + }; + + pcie-default { + + mux { + groups = "pcie_group"; + function = "pcie_func"; + }; + }; + + hdmi-default { + + mux { + groups = "hdmi_group"; + function = "hdmi_func"; + }; + }; + + rgmii0-default { + + mux { + groups = "rgmii0_group"; + function = "rgmii0_func"; + }; + }; + + rgmii1-default { + + mux { + groups = "rgmii1_group"; + function = "rgmii1_func"; + }; + }; + + spi0-default { + + mux { + groups = "spi0_group"; + function = "spi0_func"; + }; + }; + + spi1-default { + + mux { + groups = "spi1_group"; + function = "spi1_func"; + }; + }; + + spi3-default { + + mux { + groups = "spi3_group"; + function = "spi3_func"; + }; + }; + + por_time_sel0-default { + + mux { + groups = "por_time_sel0_group"; + function = "por_time_sel0_func"; + }; + }; + + por_time_sel1-default { + + mux { + groups = "por_time_sel1_group"; + function = "por_time_sel1_func"; + }; + }; + + i2s0-default { + + mux { + groups = "i2s0_group"; + function = "i2s0_func"; + }; + }; + + i2s1-default { + + mux { + groups = "i2s1_group"; + function = "i2s1_func"; + }; + }; + + i2s2-default { + + mux { + groups = "i2s2_group"; + function = "i2s2_func"; + }; + }; + + usb0_pwren-default { + + mux { + groups = "usb0_pwren_group"; + function = "usb0_pwren_func"; + }; + }; + + usb1_pwren-default { + + mux { + groups = "usb1_pwren_group"; + function = "usb1_pwren_func"; + }; + }; + + i2c0-default { + + mux { + groups = "i2c0_group"; + function = "i2c0_func"; + }; + }; + + i2c1-default { + + mux { + groups = "i2c1_group"; + function = "i2c1_func"; + }; + }; + + i2c2-default { + + mux { + groups = "i2c2_group"; + function = "i2c2_func"; + }; + }; + + i2c3-default { + + mux { + groups = "i2c3_group"; + function = "i2c3_func"; + }; + }; + + i2c4-default { + + mux { + groups = "i2c4_group"; + function = "i2c4_func"; + }; + }; + + i2c5-default { + + mux { + groups = "i2c5_group"; + function = "i2c5_func"; + }; + }; + + i2c8-default { + + mux { + groups = "i2c8_group"; + function = "i2c8_func"; + }; + }; + + i2c10-default { + + mux { + groups = "i2c10_group"; + function = "i2c10_func"; + }; + }; + + i2c11-default { + + mux { + groups = "i2c11_group"; + function = "i2c11_func"; + }; + }; + + uart0-default { + + mux { + groups = "uart0_group"; + function = "uart0_func"; + }; + }; + + uart1-default { + + mux { + groups = "uart1_group"; + function = "uart1_func"; + }; + }; + + uart2-default { + + mux { + groups = "uart2_group"; + function = "uart2_func"; + }; + }; + + pwm0-default { + phandle = <0x4e>; + + mux { + groups = "pwm0_group"; + function = "pwm0_func"; + }; + }; + + fan_tach-default { + phandle = <0x2d>; + + mux { + groups = "fan_tach_group"; + function = "fan_tach_func"; + }; + }; + + mipi_csi0-default { + + mux { + groups = "mipi_csi0_group"; + function = "mipi_csi0_func"; + }; + }; + + mipi_csi1-default { + + mux { + groups = "mipi_csi1_group"; + function = "mipi_csi1_func"; + }; + }; + + mipi_csi2-default { + + mux { + groups = "mipi_csi2_group"; + function = "mipi_csi2_func"; + }; + }; + + mipi_csi3-default { + + mux { + groups = "mipi_csi3_group"; + function = "mipi_csi3_func"; + }; + }; + + mipi_csi4-default { + + mux { + groups = "mipi_csi4_group"; + function = "mipi_csi4_func"; + }; + }; + + mipi_csi5-default { + + mux { + groups = "mipi_csi5_group"; + function = "mipi_csi5_func"; + }; + }; + + s_mode-default { + + mux { + groups = "s_mode_group"; + function = "s_mode_func"; + }; + }; + + pinmux_ddr_refclk_sel-default { + + mux { + groups = "pinmux_ddr_refclk_sel_group"; + function = "pinmux_ddr_refclk_sel_func"; + }; + }; + + boot_sel-default { + + mux { + groups = "boot_sel_group"; + function = "boot_sel_func"; + }; + }; + + lpddr_ref_clk-default { + + mux { + groups = "lpddr_ref_clk_group"; + function = "lpddr_ref_clk_func"; + }; + }; + + spi2-default { + + mux1 { + groups = "spi2_clk_group"; + function = "spi2_clk_func"; + }; + + conf1 { + groups = "spi2_clk_group"; + input-enable = <0x01>; + bias-pull-up = <0x01>; + bias-pull-down = <0x00>; + }; + + mux2 { + groups = "spi2_d0_group"; + function = "spi2_d0_func"; + }; + + conf2 { + groups = "spi2_d0_group"; + input-enable = <0x01>; + bias-pull-up = <0x01>; + bias-pull-down = <0x00>; + }; + + mux3 { + groups = "spi2_d1_d2_d3_group"; + function = "spi2_d1_d2_d3_func"; + }; + + conf3 { + groups = "spi2_d1_d2_d3_group"; + input-enable = <0x01>; + bias-pull-up = <0x01>; + bias-pull-down = <0x00>; + }; + + mux4 { + groups = "spi2_cs_group"; + function = "spi2_cs_func"; + }; + }; + + sata_act_led-default { + phandle = <0x26>; + + mux { + groups = "sata_act_led_group"; + function = "sata_act_led_func"; + }; + + conf { + groups = "sata_act_led_group"; + input-enable = <0x00>; + bias-pull-down = <0x01>; + }; + }; + + emmc_led_control-default { + phandle = <0x28>; + + mux { + groups = "emmc_led_control_group"; + function = "emmc_led_control_func"; + }; + + conf { + groups = "emmc_led_control_group"; + input-enable = <0x00>; + bias-pull-down = <0x01>; + }; + }; + + sd0_led_control-default { + + mux { + groups = "sd0_led_control_group"; + function = "sd0_led_control_func"; + }; + }; + + sd1_led_control-default { + + mux { + groups = "sd1_led_control_group"; + function = "sd1_led_control_func"; + }; + }; + + i2c6-default { + + mux { + groups = "i2c6_group"; + function = "i2c6_func"; + }; + }; + + i2c7-default { + + mux { + groups = "i2c7_group"; + function = "i2c7_func"; + }; + }; + + i2c9-default { + + mux { + groups = "i2c9_group"; + function = "i2c9_func"; + }; + }; + + pwm1-default { + + mux { + groups = "pwm1_group"; + function = "pwm1_func"; + }; + }; + + pwm2-default { + + mux { + groups = "pwm2_group"; + function = "pwm2_func"; + }; + }; + + mipi_csi_xtrig-default { + + mux { + groups = "mipi_csi_xtrig_group"; + function = "mipi_csi_xtrig_func"; + }; + }; + + uart3-default { + + mux { + groups = "uart3_group"; + function = "uart3_func"; + }; + }; + + uart4-default { + + mux { + groups = "uart4_group"; + function = "uart4_func"; + }; + }; + + gpio0-default { + phandle = <0x2e>; + + mux { + groups = "gpio0_group"; + function = "gpio0_func"; + }; + + conf { + groups = "gpio0_group"; + input-enable = <0x01>; + bias-pull-up = <0x01>; + }; + }; + + gpio1-default { + + mux { + groups = "gpio1_group"; + function = "gpio1_func"; + }; + }; + + gpio2-default { + + mux { + groups = "gpio2_group"; + function = "gpio2_func"; + }; + }; + + gpio3-default { + + mux { + groups = "gpio3_group"; + function = "gpio3_func"; + }; + }; + + gpio4-default { + + mux { + groups = "gpio4_group"; + function = "gpio4_func"; + }; + }; + + gpio5-default { + phandle = <0x32>; + + mux { + groups = "gpio5_group"; + function = "gpio5_func"; + }; + + conf { + groups = "gpio5_group"; + input-enable = <0x01>; + bias-pull-up = <0x01>; + }; + }; + + gpio6-default { + phandle = <0x33>; + + mux { + groups = "gpio6_group"; + function = "gpio6_func"; + }; + + conf { + groups = "gpio6_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio7-default { + phandle = <0x34>; + + mux { + groups = "gpio7_group"; + function = "gpio7_func"; + }; + + conf { + groups = "gpio7_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio8-default { + phandle = <0x35>; + + mux { + groups = "gpio8_group"; + function = "gpio8_func"; + }; + + conf { + groups = "gpio8_group"; + input-enable = <0x01>; + bias-pull-up = <0x01>; + }; + }; + + gpio9-default { + phandle = <0x36>; + + mux { + groups = "gpio9_group"; + function = "gpio9_func"; + }; + + conf { + groups = "gpio9_group"; + input-enable = <0x01>; + bias-pull-up = <0x01>; + }; + }; + + gpio10-default { + phandle = <0x37>; + + mux { + groups = "gpio10_group"; + function = "gpio10_func"; + }; + + conf { + groups = "gpio10_group"; + input-enable = <0x01>; + bias-pull-up = <0x01>; + }; + }; + + gpio11-default { + + mux { + groups = "gpio11_group"; + function = "gpio11_func"; + }; + + conf { + groups = "gpio11_group"; + input-enable = <0x01>; + bias-pull-up = <0x01>; + }; + }; + + gpio12-default { + + mux { + groups = "gpio12_group"; + function = "gpio12_func"; + }; + }; + + gpio13-default { + + mux { + groups = "gpio13_group"; + function = "gpio13_func"; + }; + }; + + gpio14-default { + + mux { + groups = "gpio14_group"; + function = "gpio14_func"; + }; + }; + + gpio15-default { + + mux { + groups = "gpio15_group"; + function = "gpio15_func"; + }; + }; + + gpio16-default { + + mux { + groups = "gpio16_group"; + function = "gpio16_func"; + }; + + conf { + groups = "gpio16_group"; + input-enable = <0x00>; + bias-pull-down = <0x01>; + }; + }; + + gpio17-default { + phandle = <0x38>; + + mux { + groups = "gpio17_group"; + function = "gpio17_func"; + }; + + conf { + groups = "gpio17_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio18-default { + + mux { + groups = "gpio18_group"; + function = "gpio18_func"; + }; + + conf { + groups = "gpio18_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio19-default { + + mux { + groups = "gpio19_group"; + function = "gpio19_func"; + }; + + conf { + groups = "gpio19_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio20-default { + + mux { + groups = "gpio20_group"; + function = "gpio20_func"; + }; + + conf { + groups = "gpio20_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio21-default { + + mux { + groups = "gpio21_group"; + function = "gpio21_func"; + }; + + conf { + groups = "gpio21_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio22-default { + + mux { + groups = "gpio22_group"; + function = "gpio22_func"; + }; + }; + + gpio23-default { + + mux { + groups = "gpio23_group"; + function = "gpio23_func"; + }; + }; + + gpio24-default { + + mux { + groups = "gpio24_group"; + function = "gpio24_func"; + }; + }; + + gpio25-default { + + mux { + groups = "gpio25_group"; + function = "gpio25_func"; + }; + }; + + gpio26-default { + + mux { + groups = "gpio26_group"; + function = "gpio26_func"; + }; + }; + + gpio27-default { + + mux { + groups = "gpio27_group"; + function = "gpio27_func"; + }; + }; + + gpio28-default { + phandle = <0x2f>; + + mux { + groups = "gpio28_group"; + function = "gpio28_func"; + }; + + conf { + groups = "gpio28_group"; + input-enable = <0x01>; + bias-pull-up = <0x01>; + }; + }; + + gpio29-default { + + mux { + groups = "gpio29_group"; + function = "gpio29_func"; + }; + }; + + gpio30-default { + + mux { + groups = "gpio30_group"; + function = "gpio30_func"; + }; + }; + + gpio31-default { + + mux { + groups = "gpio31_group"; + function = "gpio31_func"; + }; + }; + + gpio32-default { + + mux { + groups = "gpio32_group"; + function = "gpio32_func"; + }; + }; + + gpio33-default { + + mux { + groups = "gpio33_group"; + function = "gpio33_func"; + }; + }; + + gpio34-default { + + mux { + groups = "gpio34_group"; + function = "gpio34_func"; + }; + }; + + gpio35-default { + phandle = <0x39>; + + mux { + groups = "gpio35_group"; + function = "gpio35_func"; + }; + + conf { + groups = "gpio35_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio36-default { + phandle = <0x3a>; + + mux { + groups = "gpio36_group"; + function = "gpio36_func"; + }; + + conf { + groups = "gpio36_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio37-default { + phandle = <0x3b>; + + mux { + groups = "gpio37_group"; + function = "gpio37_func"; + }; + + conf { + groups = "gpio37_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio38-default { + phandle = <0x3c>; + + mux { + groups = "gpio38_group"; + function = "gpio38_func"; + }; + + conf { + groups = "gpio38_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio39-default { + phandle = <0x3d>; + + mux { + groups = "gpio39_group"; + function = "gpio39_func"; + }; + + conf { + groups = "gpio39_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio40-default { + phandle = <0x3e>; + + mux { + groups = "gpio40_group"; + function = "gpio40_func"; + }; + + conf { + groups = "gpio40_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio41-default { + phandle = <0x3f>; + + mux { + groups = "gpio41_group"; + function = "gpio41_func"; + }; + }; + + gpio42-default { + + mux { + groups = "gpio42_group"; + function = "gpio42_func"; + }; + + conf { + groups = "gpio42_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio43-default { + phandle = <0x60>; + + mux { + groups = "gpio43_group"; + function = "gpio43_func"; + }; + }; + + gpio44-default { + + mux { + groups = "gpio44_group"; + function = "gpio44_func"; + }; + }; + + gpio45-default { + + mux { + groups = "gpio45_group"; + function = "gpio45_func"; + }; + }; + + gpio46-default { + phandle = <0x40>; + + mux { + groups = "gpio46_group"; + function = "gpio46_func"; + }; + + conf { + groups = "gpio46_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio47-default { + + mux { + groups = "gpio47_group"; + function = "gpio47_func"; + }; + + conf { + groups = "gpio47_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio48-default { + + mux { + groups = "gpio48_group"; + function = "gpio48_func"; + }; + }; + + gpio49-default { + + mux { + groups = "gpio49_group"; + function = "gpio49_func"; + }; + }; + + gpio50-default { + + mux { + groups = "gpio50_group"; + function = "gpio50_func"; + }; + }; + + gpio51-default { + + mux { + groups = "gpio51_group"; + function = "gpio51_func"; + }; + }; + + gpio52-default { + phandle = <0x41>; + + mux { + groups = "gpio52_group"; + function = "gpio52_func"; + }; + + conf { + groups = "gpio52_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio53-default { + phandle = <0x42>; + + mux { + groups = "gpio53_group"; + function = "gpio53_func"; + }; + + conf { + groups = "gpio53_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio54-default { + + mux { + groups = "gpio54_group"; + function = "gpio54_func"; + }; + }; + + gpio55-default { + + mux { + groups = "gpio55_group"; + function = "gpio55_func"; + }; + }; + + gpio56-default { + + mux { + groups = "gpio56_group"; + function = "gpio56_func"; + }; + }; + + gpio57-default { + + mux { + groups = "gpio57_group"; + function = "gpio57_func"; + }; + }; + + gpio58-default { + + mux { + groups = "gpio58_group"; + function = "gpio58_func"; + }; + }; + + gpio59-default { + + mux { + groups = "gpio59_group"; + function = "gpio59_func"; + }; + }; + + gpio60-default { + + mux { + groups = "gpio60_group"; + function = "gpio60_func"; + }; + }; + + gpio61-default { + + mux { + groups = "gpio61_group"; + function = "gpio61_func"; + }; + }; + + gpio62-default { + + mux { + groups = "gpio62_group"; + function = "gpio62_func"; + }; + }; + + gpio63-default { + + mux { + groups = "gpio63_group"; + function = "gpio63_func"; + }; + }; + + gpio64-default { + phandle = <0x43>; + + mux { + groups = "gpio64_group"; + function = "gpio64_func"; + }; + + conf { + groups = "gpio64_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio65-default { + phandle = <0x44>; + + mux { + groups = "gpio65_group"; + function = "gpio65_func"; + }; + + conf { + groups = "gpio65_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio66-default { + phandle = <0x45>; + + mux { + groups = "gpio66_group"; + function = "gpio66_func"; + }; + + conf { + groups = "gpio66_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio67-default { + phandle = <0x46>; + + mux { + groups = "gpio67_group"; + function = "gpio67_func"; + }; + + conf { + groups = "gpio67_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio68-default { + + mux { + groups = "gpio68_group"; + function = "gpio68_func"; + }; + }; + + gpio69-default { + + mux { + groups = "gpio69_group"; + function = "gpio69_func"; + }; + }; + + gpio70-default { + phandle = <0x47>; + + mux { + groups = "gpio70_group"; + function = "gpio70_func"; + }; + }; + + gpio71-default { + + mux { + groups = "gpio71_group"; + function = "gpio71_func"; + }; + }; + + gpio72-default { + + mux { + groups = "gpio72_group"; + function = "gpio72_func"; + }; + }; + + gpio73-default { + phandle = <0x48>; + + mux { + groups = "gpio73_group"; + function = "gpio73_func"; + }; + }; + + gpio74-default { + + mux { + groups = "gpio74_group"; + function = "gpio74_func"; + }; + }; + + gpio75-default { + + mux { + groups = "gpio75_group"; + function = "gpio75_func"; + }; + }; + + gpio76-default { + + mux { + groups = "gpio76_group"; + function = "gpio76_func"; + }; + }; + + gpio77-default { + + mux { + groups = "gpio77_group"; + function = "gpio77_func"; + }; + }; + + gpio78-default { + + mux { + groups = "gpio78_group"; + function = "gpio78_func"; + }; + }; + + gpio79-default { + + mux { + groups = "gpio79_group"; + function = "gpio79_func"; + }; + }; + + gpio80-default { + + mux { + groups = "gpio80_group"; + function = "gpio80_func"; + }; + }; + + gpio81-default { + + mux { + groups = "gpio81_group"; + function = "gpio81_func"; + }; + }; + + gpio82-default { + phandle = <0x5a>; + + mux { + groups = "gpio82_group"; + function = "gpio82_func"; + }; + }; + + gpio83-default { + phandle = <0x49>; + + mux { + groups = "gpio83_group"; + function = "gpio83_func"; + }; + }; + + gpio84-default { + + mux { + groups = "gpio84_group"; + function = "gpio84_func"; + }; + }; + + gpio85-default { + phandle = <0x5b>; + + mux { + groups = "gpio85_group"; + function = "gpio85_func"; + }; + }; + + gpio86-default { + phandle = <0x4a>; + + mux { + groups = "gpio86_group"; + function = "gpio86_func"; + }; + }; + + gpio87-default { + phandle = <0x4b>; + + mux { + groups = "gpio87_group"; + function = "gpio87_func"; + }; + }; + + gpio88-default { + + mux { + groups = "gpio88_group"; + function = "gpio88_func"; + }; + }; + + gpio89-default { + + mux { + groups = "gpio89_group"; + function = "gpio89_func"; + }; + }; + + gpio90-default { + + mux { + groups = "gpio90_group"; + function = "gpio90_func"; + }; + }; + + gpio91-default { + + mux { + groups = "gpio91_group"; + function = "gpio91_func"; + }; + }; + + gpio92-default { + phandle = <0x4c>; + + mux { + groups = "gpio92_group"; + function = "gpio92_func"; + }; + + conf { + groups = "gpio92_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio93-default { + phandle = <0x4d>; + + mux { + groups = "gpio93_group"; + function = "gpio93_func"; + }; + + conf { + groups = "gpio93_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio94-default { + + mux { + groups = "gpio94_group"; + function = "gpio94_func"; + }; + + conf { + groups = "gpio94_group"; + input-enable = <0x00>; + bias-pull-down = <0x01>; + }; + }; + + gpio95-default { + + mux { + groups = "gpio95_group"; + function = "gpio95_func"; + }; + }; + + gpio96-default { + + mux { + groups = "gpio96_group"; + function = "gpio96_func"; + }; + }; + + gpio97-default { + + mux { + groups = "gpio97_group"; + function = "gpio97_func"; + }; + }; + + gpio98-default { + + mux { + groups = "gpio98_group"; + function = "gpio98_func"; + }; + }; + + gpio99-default { + + mux { + groups = "gpio99_group"; + function = "gpio99_func"; + }; + }; + + gpio100-default { + + mux { + groups = "gpio100_group"; + function = "gpio100_func"; + }; + }; + + gpio101-default { + + mux { + groups = "gpio101_group"; + function = "gpio101_func"; + }; + }; + + gpio102-default { + + mux { + groups = "gpio102_group"; + function = "gpio102_func"; + }; + }; + + gpio103-default { + + mux { + groups = "gpio103_group"; + function = "gpio103_func"; + }; + }; + + gpio104-default { + + mux { + groups = "gpio104_group"; + function = "gpio104_func"; + }; + }; + + gpio105-default { + + mux { + groups = "gpio105_group"; + function = "gpio105_func"; + }; + }; + + gpio106-default { + phandle = <0x1b>; + + mux { + groups = "gpio106_group"; + function = "gpio106_func"; + }; + + conf { + groups = "gpio106_group"; + input-enable = <0x00>; + bias-pull-down = <0x01>; + }; + }; + + gpio107-default { + + mux { + groups = "gpio107_group"; + function = "gpio107_func"; + }; + + conf { + groups = "gpio107_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio108-default { + + mux { + groups = "gpio108_group"; + function = "gpio108_func"; + }; + + conf { + groups = "gpio108_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio109-default { + + mux { + groups = "gpio109_group"; + function = "gpio109_func"; + }; + + conf { + groups = "gpio109_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio110-default { + + mux { + groups = "gpio110_group"; + function = "gpio110_func"; + }; + + conf { + groups = "gpio110_group"; + input-enable = <0x01>; + bias-pull-down = <0x01>; + }; + }; + + gpio111-default { + phandle = <0x1f>; + + mux { + groups = "gpio111_group"; + function = "gpio111_func"; + }; + + conf { + groups = "gpio111_group"; + input-enable = <0x00>; + bias-pull-up = <0x01>; + }; + }; + + csi_mon_out-default { + + mux { + groups = "csi_mon_out_group"; + function = "csi_mon_out_func"; + }; + }; + + csi_ocla_clk-default { + + mux { + groups = "csi_ocla_clk_group"; + function = "csi_ocla_clk_func"; + }; + }; + + csi_mon_out_valid-default { + + mux { + groups = "csi_mon_out_valid_group"; + function = "csi_mon_out_valid_func"; + }; + }; + + csi_parity_error-default { + + mux { + groups = "csi_parity_error_group"; + function = "csi_parity_error_func"; + }; + }; + + csi_dtb_out-default { + + mux { + groups = "csi_dtb_out_group"; + function = "csi_dtb_out_func"; + }; + }; + + csi_phy_sel-default { + + mux { + groups = "csi_phy_sel_group"; + function = "csi_phy_sel_func"; + }; + }; + + vc_g2d0_debug_out-default { + + mux { + groups = "vc_g2d0_debug_out_group"; + function = "vc_g2d0_debug_out_func"; + }; + }; + + vc_g2d1_debug_out-default { + + mux { + groups = "vc_g2d1_debug_out_group"; + function = "vc_g2d1_debug_out_func"; + }; + }; + + sata_mpll_clk-default { + + mux { + groups = "sata_mpll_clk_group"; + function = "sata_mpll_clk_func"; + }; + }; + + sata_ref_repeat_clk_m-default { + + mux { + groups = "sata_ref_repeat_clk_m_group"; + function = "sata_ref_repeat_clk_m_func"; + }; + }; + + sata_ref_repeat_clk_p-default { + + mux { + groups = "sata_ref_repeat_clk_p_group"; + function = "sata_ref_repeat_clk_p_func"; + }; + }; + }; + + gpio@51600000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "snps,dw-apb-gpio"; + reg = <0x00 0x51600000 0x00 0x80>; + status = "okay"; + + gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <0x02>; + ngpios = <0x20>; + reg = <0x00>; + interrupt-parent = <0x0f>; + interrupts = <0x12f 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0x138 0x139 0x13a 0x13b 0x13c 0x13d 0x13e 0x13f 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14a 0x14b 0x14c 0x14d 0x14e>; + phandle = <0x30>; + }; + + gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <0x02>; + ngpios = <0x20>; + reg = <0x01>; + phandle = <0x61>; + }; + + gpio-port@2 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <0x02>; + ngpios = <0x20>; + reg = <0x02>; + phandle = <0x5c>; + }; + + gpio-port@3 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <0x02>; + ngpios = <0x10>; + reg = <0x03>; + phandle = <0x1c>; + }; + }; + + pwm@0x50818000 { + compatible = "eswin,pwm-eswin"; + #pwm-cells = <0x02>; + reg = <0x00 0x50818000 0x00 0x4000>; + clock-names = "pwm", "pclk"; + clocks = <0x03 0x2a6>; + clock-frequency = <0xbebc200>; + resets = <0x17 0x0f 0x01>; + reset-names = "pwmrst"; + pinctrl-names = "default"; + pinctrl-0 = <0x4e>; + status = "okay"; + phandle = <0x2c>; + }; + + watchdog@0x50800000 { + compatible = "snps,dw-wdt"; + reg = <0x00 0x50800000 0x00 0x4000>; + clocks = <0x03 0x298>; + clock-names = "pclk"; + resets = <0x17 0x11 0x01>; + reset-names = "rst"; + interrupts = <0x57>; + interrupt-parent = <0x0f>; + status = "okay"; + }; + + watchdog@0x50804000 { + compatible = "snps,dw-wdt"; + reg = <0x00 0x50804000 0x00 0x4000>; + clocks = <0x03 0x299>; + clock-names = "pclk"; + resets = <0x17 0x11 0x02>; + reset-names = "rst"; + interrupts = <0x58>; + interrupt-parent = <0x0f>; + status = "okay"; + }; + + watchdog@0x50808000 { + compatible = "snps,dw-wdt"; + reg = <0x00 0x50808000 0x00 0x4000>; + clocks = <0x03 0x29a>; + clock-names = "pclk"; + resets = <0x17 0x11 0x04>; + reset-names = "rst"; + interrupts = <0x59>; + interrupt-parent = <0x0f>; + status = "okay"; + }; + + watchdog@0x5080c000 { + compatible = "snps,dw-wdt"; + reg = <0x00 0x5080c000 0x00 0x4000>; + clocks = <0x03 0x29b>; + clock-names = "pclk"; + resets = <0x17 0x11 0x08>; + reset-names = "rst"; + interrupts = <0x5a>; + interrupt-parent = <0x0f>; + status = "okay"; + }; + + timer@0x51840000 { + compatible = "eswin,eswin-timer"; + #address-cells = <0x02>; + #size-cells = <0x02>; + reg = <0x00 0x51840000 0x00 0x8000>; + perf_count = <0x07>; + interrupt-parent = <0x0f>; + interrupts = <0x159>; + clock-names = "pclk", "timer_aclk"; + clocks = <0x03 0x26c 0x03 0x268>; + resets = <0x17 0x30 0x01 0x17 0x30 0x02 0x17 0x30 0x04 0x17 0x30 0x08 0x17 0x30 0x10 0x17 0x30 0x20 0x17 0x30 0x40 0x17 0x30 0x80 0x17 0x30 0x100>; + reset-names = "trst0", "trst1", "trst2", "trst3", "trst4", "trst5", "trst6", "trst7", "prst"; + status = "okay"; + }; + + timer@0x51848000 { + compatible = "eswin,eswin-timer"; + #address-cells = <0x02>; + #size-cells = <0x02>; + reg = <0x00 0x51848000 0x00 0x8000>; + interrupt-parent = <0x0f>; + interrupts = <0x15a>; + clock-names = "pclk", "timer_aclk"; + clocks = <0x03 0x26d 0x03 0x269>; + resets = <0x17 0x31 0x01 0x17 0x31 0x02 0x17 0x31 0x04 0x17 0x31 0x08 0x17 0x31 0x10 0x17 0x31 0x20 0x17 0x31 0x40 0x17 0x31 0x80 0x17 0x31 0x100>; + reset-names = "trst0", "trst1", "trst2", "trst3", "trst4", "trst5", "trst6", "trst7", "prst"; + status = "okay"; + }; + + timer@0x51850000 { + compatible = "eswin,eswin-timer"; + #address-cells = <0x02>; + #size-cells = <0x02>; + reg = <0x00 0x51850000 0x00 0x8000>; + interrupt-parent = <0x0f>; + interrupts = <0x15b>; + clock-names = "pclk", "timer_aclk"; + clocks = <0x03 0x26e 0x03 0x26a>; + resets = <0x17 0x32 0x01 0x17 0x32 0x02 0x17 0x32 0x04 0x17 0x32 0x08 0x17 0x32 0x10 0x17 0x32 0x20 0x17 0x32 0x40 0x17 0x32 0x80 0x17 0x32 0x100>; + reset-names = "trst0", "trst1", "trst2", "trst3", "trst4", "trst5", "trst6", "trst7", "prst"; + status = "okay"; + }; + + timer@0x51858000 { + compatible = "eswin,eswin-timer"; + #address-cells = <0x02>; + #size-cells = <0x02>; + reg = <0x00 0x51858000 0x00 0x8000>; + interrupt-parent = <0x0f>; + interrupts = <0x15c>; + clock-names = "pclk", "timer_aclk", "timer3_clk8"; + clocks = <0x03 0x26f 0x03 0x26b 0x03 0x270>; + resets = <0x17 0x33 0x01 0x17 0x33 0x02 0x17 0x33 0x04 0x17 0x33 0x08 0x17 0x33 0x10 0x17 0x33 0x20 0x17 0x33 0x40 0x17 0x33 0x80 0x17 0x33 0x100>; + reset-names = "trst0", "trst1", "trst2", "trst3", "trst4", "trst5", "trst6", "trst7", "prst"; + status = "okay"; + }; + + rtc@51818000 { + compatible = "eswin,eic7700-rtc"; + reg = <0x00 0x51818000 0x00 0x400>; + eswin,syscfg = <0x16 0x3c0>; + interrupt-parent = <0x0f>; + interrupts = <0x124>; + clocks = <0x03 0x272>; + clock-names = "rtcclk"; + clock-frequency = <0x3d09>; + resets = <0x17 0x34 0x01>; + reset-names = "rtcrst"; + status = "okay"; + }; + + i2s0@50200000 { + compatible = "snps,i2s"; + clocks = <0x03 0x250>; + clock-names = "mclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + #sound-dai-cells = <0x00>; + reg = <0x00 0x50200000 0x00 0x10000>; + dma-names = "rx", "tx"; + dmas = <0x27 0x04 0x00 0x27 0x05 0x00>; + vo_mclk_sel,syscrg = <0x15 0x1bc>; + resets = <0x17 0x22 0x01 0x17 0x22 0x02 0x17 0x21 0x02>; + reset-names = "i2srst", "i2sprst", "voprst"; + status = "okay"; + + port { + phandle = <0x52>; + + endpoint { + remote-endpoint = <0x4f>; + dai-format = "i2s"; + phandle = <0x5f>; + }; + }; + }; + + i2s1@50210000 { + compatible = "snps,i2s"; + clocks = <0x03 0x250>; + clock-names = "mclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + #sound-dai-cells = <0x00>; + reg = <0x00 0x50210000 0x00 0x10000>; + dma-names = "rx", "tx"; + dmas = <0x27 0x02 0x01 0x27 0x03 0x01>; + vo_mclk_sel,syscrg = <0x15 0x1bc>; + resets = <0x17 0x22 0x01 0x17 0x22 0x02 0x17 0x21 0x02>; + reset-names = "i2srst", "i2sprst", "voprst"; + status = "okay"; + + port { + phandle = <0x51>; + + endpoint { + remote-endpoint = <0x50>; + dai-format = "i2s"; + phandle = <0x31>; + }; + }; + }; + + i2s2@50220000 { + compatible = "snps,i2s"; + clocks = <0x03 0x250>; + clock-names = "mclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + #sound-dai-cells = <0x00>; + reg = <0x00 0x50220000 0x00 0x10000>; + dma-names = "rx", "tx"; + dmas = <0x27 0x00 0x02 0x27 0x01 0x02>; + vo_mclk_sel,syscrg = <0x15 0x1bc>; + resets = <0x17 0x22 0x01 0x17 0x22 0x02 0x17 0x21 0x02>; + reset-names = "i2srst", "i2sprst", "voprst"; + status = "disabled"; + }; + + graphcard0 { + compatible = "audio-graph-card"; + status = "okay"; + dais = <0x51>; + }; + + graphcard1 { + compatible = "audio-graph-card"; + status = "okay"; + dais = <0x52>; + }; + + graphcard2 { + compatible = "audio-graph-card"; + status = "disabled"; + }; + + display-subsystem { + compatible = "eswin,display-subsystem"; + ports = <0x53>; + status = "okay"; + }; + + dvb-subsystem { + compatible = "amlogic,dvb_widgets"; + status = "disabled"; + }; + + display_control@502c0000 { + compatible = "eswin,dc"; + reg = <0x00 0x502c0000 0x00 0x100 0x00 0x502c0180 0x00 0x700 0x00 0x502c1400 0x00 0x1400>; + interrupt-parent = <0x0f>; + interrupts = <0xee>; + clocks = <0x03 0x24d 0x03 0x24f 0x03 0x24c 0x03 0x04 0x03 0x2a>; + clock-names = "cfg_clk", "pix_clk", "axi_clk", "spll0_fout1", "vo_mux"; + resets = <0x17 0x23 0x01 0x17 0x23 0x02 0x17 0x23 0x04 0x17 0x23 0x08>; + reset-names = "vo_arst", "vo_prst", "dc_arst", "dc_prst"; + status = "okay"; + + port { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x53>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x54>; + phandle = <0x58>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x55>; + phandle = <0x57>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x56>; + phandle = <0x5e>; + }; + }; + }; + + es_wb { + compatible = "eswin,virtual_display"; + bpp = [08]; + status = "disabled"; + + port { + + endpoint { + remote-endpoint = <0x57>; + phandle = <0x55>; + }; + }; + }; + + dsi-output { + compatible = "eswin,dsi-encoder"; + status = "okay"; + }; + + mipi_dsi@50270000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "eswin,dsi"; + reg = <0x00 0x50270000 0x00 0x10000>; + clocks = <0x03 0x201>; + clock-names = "pclk"; + resets = <0x17 0x21 0x01>; + reset-names = "phyrstn"; + status = "okay"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00>; + + endpoint { + remote-endpoint = <0x58>; + phandle = <0x54>; + }; + }; + + port@1 { + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x01>; + + endpoint { + remote-endpoint = <0x59>; + phandle = <0x5d>; + }; + }; + }; + + dsi_panel@0 { + compatible = "eswin,generic-panel"; + reg = <0x00>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x5a 0x5b>; + backlight0-gpios = <0x5c 0x12 0x00>; + rst-gpios = <0x5c 0x15 0x00>; + + port { + + endpoint { + remote-endpoint = <0x5d>; + phandle = <0x59>; + }; + }; + }; + }; + + dctest@502c0000 { + compatible = "eswin,dc"; + reg = <0x00 0x502c0000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0xee>; + status = "disabled"; + }; + + hdmi@502a0000 { + compatible = "eswin,eswin-dw-hdmi"; + reg = <0x00 0x502a0000 0x00 0x20000>; + pinctrl-names = "default"; + interrupt-parent = <0x0f>; + interrupts = <0x112>; + clocks = <0x03 0x24d 0x03 0x252 0x03 0x251>; + clock-names = "iahb", "cec", "isfr"; + reg-io-width = <0x04>; + ddc-i2c-scl-high-time-ns = <0x1264>; + ddc-i2c-scl-low-time-ns = <0x1334>; + #sound-dai-cells = <0x00>; + resets = <0x17 0x21 0x08 0x17 0x21 0x10 0x17 0x21 0x20>; + reset-names = "prstn", "phyrstn", "rstn"; + status = "okay"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint@0 { + remote-endpoint = <0x5e>; + phandle = <0x56>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint@1 { + system-clock-frequency = <0xbb8000>; + remote-endpoint = <0x5f>; + phandle = <0x4f>; + }; + }; + }; + }; + + hdmi-hdcp2@50290000 { + compatible = "eswin,dw-hdmi-hdcp2"; + reg = <0x00 0x50290000 0x00 0x10000>; + interrupt-parent = <0x0f>; + interrupts = <0x113>; + clocks = <0x03 0x24d 0x03 0x24e>; + clock-names = "pclk_hdcp2", "hdcp2_clk_hdmi"; + dma-noncoherent; + status = "okay"; + }; + + usb0@50480000 { + compatible = "eswin,eic7700-dwc3"; + #address-cells = <0x02>; + #size-cells = <0x02>; + clocks = <0x03 0x10e>; + clock-names = "suspend"; + eswin,hsp_sp_csr = <0x19 0x800 0x808 0x83c 0x840>; + resets = <0x17 0x07 0x8000>; + reset-names = "vaux"; + ranges; + status = "okay"; + + dwc3@50480000 { + compatible = "snps,dwc3"; + reg = <0x00 0x50480000 0x00 0x10000>; + #address-cells = <0x02>; + #size-cells = <0x02>; + interrupt-parent = <0x0f>; + interrupts = <0x55>; + interrupt-names = "peripheral"; + dr_mode = "host"; + phy_type = "utmi"; + maximum-speed = "super-speed"; + iommus = <0x18 0x0a>; + eswin,hsp_sp_csr = <0x19 0x1044>; + dma-ranges = <0x00 0x00 0x00 0xc0000000 0x200 0x00>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,parkmode-disable-ss-quirk; + status = "okay"; + numa-node-id = <0x00>; + tbus = <0x02>; + }; + }; + + usb1@50490000 { + compatible = "eswin,eic7700-dwc3"; + #address-cells = <0x02>; + #size-cells = <0x02>; + clocks = <0x03 0x10f>; + clock-names = "suspend"; + eswin,hsp_sp_csr = <0x19 0x900 0x908 0x93c 0x940>; + resets = <0x17 0x07 0x10000>; + reset-names = "vaux"; + ranges; + status = "okay"; + + dwc3@50490000 { + compatible = "snps,dwc3"; + reg = <0x00 0x50490000 0x00 0x10000>; + #address-cells = <0x02>; + #size-cells = <0x02>; + interrupt-parent = <0x0f>; + interrupts = <0x56>; + interrupt-names = "host"; + dr_mode = "host"; + phy_type = "utmi"; + maximum-speed = "super-speed"; + iommus = <0x18 0x0b>; + eswin,hsp_sp_csr = <0x19 0x1048>; + dma-ranges = <0x00 0x00 0x00 0xc0000000 0x200 0x00>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,parkmode-disable-ss-quirk; + status = "okay"; + numa-node-id = <0x00>; + tbus = <0x02>; + + usb-hub { + gpio-hog; + pinctrl-names = "default"; + pinctrl-0 = <0x60>; + gpios = <0x61 0x0b 0x00>; + output-low; + line-name = "usb-hub-reset"; + }; + }; + }; + + vi_common_top_csr@0x51030000 { + compatible = "esw,vi-common-csr", "syscon"; + clocks = <0x03 0x23f 0x03 0x241 0x03 0x243 0x03 0x240 0x03 0x24b 0x03 0x24a 0x03 0x244 0x03 0x245 0x03 0x246 0x03 0x247 0x03 0x248 0x03 0x249 0x03 0x27 0x03 0x28 0x03 0x29 0x03 0x04 0x03 0x0d>; + clock-names = "aclk", "cfg_clk", "isp_aclk", "dvp_clk", "phy_cfg", "phy_escclk", "sht0", "sht1", "sht2", "sht3", "sht4", "sht5", "aclk_mux", "dvp_mux", "isp_mux", "spll0_fout1", "vpll_fout1"; + resets = <0x17 0x1c 0x01 0x17 0x1c 0x02 0x17 0x1e 0x01 0x17 0x1f 0x01 0x17 0x1d 0x01 0x17 0x20 0x01 0x17 0x20 0x02 0x17 0x20 0x04 0x17 0x20 0x08 0x17 0x20 0x10 0x17 0x20 0x20>; + reset-names = "axi", "cfg", "isp0", "isp1", "dvp", "sht0", "sht1", "sht2", "sht3", "sht4", "sht5"; + id = <0x00>; + #size-cells = <0x02>; + reg = <0x00 0x51030000 0x00 0x10000>; + phandle = <0x62>; + }; + + isp@0x51000000 { + compatible = "esw,eic7700-isp"; + reg = <0x00 0x51000000 0x00 0x10000>; + interrupts = <0x15 0x13 0x14>; + interrupt-parent = <0x0f>; + id = <0x00>; + #size-cells = <0x02>; + dma-ranges = <0x00 0x20000000 0x00 0x80000000 0x00 0x40000000>; + iommus = <0x18 0x06>; + tbus = <0x00>; + eswin,vi_top_csr = <0x62 0x1000>; + numa-node-id = <0x00>; + status = "disabled"; + }; + + isp@0x51010000 { + compatible = "esw,eic7700-isp"; + reg = <0x00 0x51010000 0x00 0x10000>; + interrupts = <0x18 0x16 0x17>; + interrupt-parent = <0x0f>; + id = <0x01>; + #size-cells = <0x02>; + dma-ranges = <0x00 0x20000000 0x00 0x80000000 0x00 0x40000000>; + tbus = <0x00>; + eswin,vi_top_csr = <0x62 0x1004>; + numa-node-id = <0x00>; + status = "disabled"; + }; + + dewarp@51020000 { + compatible = "eswin,dewarp"; + clocks = <0x03 0x23f 0x03 0x241 0x03 0x242 0x03 0x27 0x03 0x54 0x03 0x04 0x03 0x0d>; + clock-names = "aclk", "cfg_clk", "dw_aclk", "aclk_mux", "dw_mux", "spll0_fout1", "vpll_fout1"; + resets = <0x17 0x1c 0x01 0x17 0x1c 0x02 0x17 0x1c 0x04>; + reset-names = "axi", "cfg", "dwe"; + interrupt-parent = <0x0f>; + interrupts = <0x1a 0x19>; + #size-cells = <0x02>; + dma-ranges = <0x00 0x20000000 0x00 0x80000000 0x00 0x40000000>; + iommus = <0x18 0x08>; + tbus = <0x00>; + eswin,vi_top_csr = <0x62 0x1008>; + reg = <0x00 0x51020000 0x00 0xc00 0x00 0x51020c00 0x00 0x120>; + numa-node-id = <0x00>; + status = "okay"; + }; + + dphy@510c0000 { + compatible = "snps,dw-dphy-rx"; + #phy-cells = <0x01>; + bus-width = <0x08>; + snps,dphy-frequency = <0x493e0>; + snps,phy_type = <0x08>; + reg = <0x00 0x510c0000 0x00 0x20000>; + numa-node-id = <0x00>; + status = "disabled"; + }; + + csidma@0x52048000 { + compatible = "eswin,csi-video"; + interrupt-parent = <0x0f>; + interrupts = <0x1d>; + reg = <0x00 0x52048000 0x00 0x1000>; + numa-node-id = <0x00>; + status = "disabled"; + + port { + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + bus-type = <0x04>; + remote-endpoint = <0x63>; + phandle = <0x65>; + }; + }; + }; + + csidma@0x52058000 { + compatible = "eswin,csi-video"; + interrupt-parent = <0x0f>; + interrupts = <0x1e>; + reg = <0x00 0x52058000 0x00 0x1000>; + numa-node-id = <0x00>; + status = "disabled"; + + port { + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + bus-type = <0x04>; + remote-endpoint = <0x64>; + phandle = <0x66>; + }; + }; + }; + + csi2@51050000 { + compatible = "snps,dw-csi"; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupt-parent = <0x0f>; + interrupts = <0x1d>; + snps,output-type = <0x00>; + reg = <0x00 0x51050000 0x00 0x1000>; + numa-node-id = <0x00>; + snps,en-ppi-width = <0x00>; + snps,en-phy-mode = <0x00>; + ipi2_en = <0x00>; + ipi2_vcid = <0x00>; + ipi3_en = <0x00>; + ipi3_vcid = <0x00>; + status = "disabled"; + + port@2 { + reg = <0x02>; + + endpoint { + bus-type = <0x05>; + remote-endpoint = <0x65>; + phandle = <0x63>; + }; + }; + }; + + csi2@51060000 { + compatible = "snps,dw-csi"; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupt-parent = <0x0f>; + interrupts = <0x1e>; + snps,output-type = <0x00>; + reg = <0x00 0x51060000 0x00 0x1000>; + numa-node-id = <0x00>; + snps,en-ppi-width = <0x00>; + snps,en-phy-mode = <0x00>; + ipi2_en = <0x00>; + ipi2_vcid = <0x00>; + ipi3_en = <0x00>; + ipi3_vcid = <0x00>; + status = "disabled"; + + port@2 { + reg = <0x02>; + + endpoint { + bus-type = <0x05>; + remote-endpoint = <0x66>; + phandle = <0x64>; + }; + }; + }; + + ddr-controller@0 { + compatible = "eswin,ddrc-1.20a"; + interrupt-parent = <0x0f>; + interrupts = <0x0a>; + interrupt-names = "ddr-ecc"; + reg = <0x00 0x52300000 0x00 0x40000>; + ctrl-id = <0x00>; + status = "okay"; + }; + + ddr-controller@1 { + compatible = "eswin,ddrc-1.20a"; + interrupt-parent = <0x0f>; + interrupts = <0x12b>; + interrupt-names = "ddr-ecc"; + reg = <0x00 0x52380000 0x00 0x40000>; + ctrl-id = <0x01>; + status = "okay"; + }; + + reset_test@1e00e000 { + compatible = "reset_test"; + resets = <0x17 0x14 0x02 0x17 0x14 0x01 0x17 0x14 0x04>; + reset-names = "bus", "core", "dbg"; + }; + }; + + opp-table0 { + compatible = "operating-points-v2"; + opp-shared; + phandle = <0x04>; + + opp-24000000 { + opp-hz = <0x00 0x16e3600>; + opp-microvolt = "", "\f5"; + clock-latency-ns = <0x11170>; + }; + + opp-100000000 { + opp-hz = <0x00 0x5f5e100>; + opp-microvolt = "", "\f5"; + clock-latency-ns = <0x11170>; + }; + + opp-200000000 { + opp-hz = <0x00 0xbebc200>; + opp-microvolt = "", "\f5"; + clock-latency-ns = <0x11170>; + }; + + opp-400000000 { + opp-hz = <0x00 0x17d78400>; + opp-microvolt = "", "\f5"; + clock-latency-ns = <0x11170>; + }; + + opp-500000000 { + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = "", "\f5"; + clock-latency-ns = <0x11170>; + }; + + opp-600000000 { + opp-hz = <0x00 0x23c34600>; + opp-microvolt = "", "\f5"; + clock-latency-ns = <0x11170>; + }; + + opp-700000000 { + opp-hz = <0x00 0x29b92700>; + opp-microvolt = "", "\f5"; + clock-latency-ns = <0x11170>; + }; + + opp-800000000 { + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = "", "\f5"; + clock-latency-ns = <0x11170>; + }; + + opp-900000000 { + opp-hz = <0x00 0x35a4e900>; + opp-microvolt = "", "\f5"; + clock-latency-ns = <0x11170>; + }; + + opp-1000000000 { + opp-hz = <0x00 0x3b9aca00>; + opp-microvolt = "", "\f5"; + clock-latency-ns = <0x11170>; + }; + + opp-1200000000 { + opp-hz = <0x00 0x47868c00>; + opp-microvolt = "", "\f5"; + clock-latency-ns = <0x11170>; + }; + + opp-1300000000 { + opp-hz = <0x00 0x4d7c6d00>; + opp-microvolt = "", "\f5"; + clock-latency-ns = <0x11170>; + }; + + opp-1400000000 { + opp-hz = <0x00 0x53724e00>; + opp-microvolt = "", "\f5"; + clock-latency-ns = <0x11170>; + }; + }; + + aliases { + serial0 = "/soc/serial@0x50900000"; + ethernet0 = "/soc/ethernet@50400000"; + ethernet1 = "/soc/ethernet@50410000"; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x20000000>; + alignment = <0x00 0x1000>; + alloc-ranges = <0x00 0x80000000 0x04 0x00>; + linux,cma-default; + }; + + sprammemory@59000000 { + no-map; + reg = <0x00 0x59000000 0x00 0x400000>; + phandle = <0x21>; + }; + + lpcpu@a0000000 { + no-map; + reg = <0x00 0xa0000000 0x00 0x100000>; + phandle = <0x2a>; + }; + + g2d_4GB_boundary_reserved_4k { + no-map; + reg = <0x00 0xfffff000 0x00 0x1000>; + }; + }; +};