ARM: Allow VMPIDR_EL2 reg to be set on unicore
Currently the seL4_VCPUReg enum only defines the seL4_VCPUReg_VMPIDR_EL2 register when the kernel is configured for SMP. This register should be available for unicore systems too as otherwise a user level VMM is not able to control the value of MPIDR_EL1 that the guest VM reads. Signed-off-by: Kent McLeod <kent@kry10.com>
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6 changed files with 8 additions and 12 deletions
6
CHANGES
6
CHANGES
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@ -83,6 +83,12 @@ Upcoming release: BREAKING
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optimization.
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* Added SMC Capability (smc_cap) and SMC forwarding for aarch64 platforms. See
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[RFC-9](https://sel4.atlassian.net/browse/RFC-9).
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* Arm+Hyp: Enabled access to seL4_VCPUReg_VMPIDR and seL4_VCPUReg_VMPIDR_EL2 for all hyp configurations.
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Previously this register was only accessible for SMP kernel configurations. Non-SMP configurations can still require
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access when wanting to control the value of MPIDR that the guest reads.
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Note that the initial value for new seL4_ARM_VCPUs for this register is 0 which isn't a legal value for MPIDR_EL1 on
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AArch64. It may be necessary for the register to be explicitly initialized by user level before launching a thread
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associated with the new seL4_ARM_VCPU.
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## Upgrade Notes
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@ -59,6 +59,7 @@
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#define ID_PFR1 " p15, 0, %0, c0, c1, 1" /* 32-bit RO CPU feature register */
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#define CPACR " p15, 0, %0, c1, c0, 2" /* 32-bit Architectural Feature Access Control Register */
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#define VMPIDR " p15, 4, %0, c0, c0, 5" /* 32-bit RW Virtualization Multiprocessor ID Register */
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#define MPIDR " p15, 0, %0, c0, c0, 5"
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/* Use Hypervisor Physical timer */
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#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
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@ -296,7 +296,6 @@ static inline void set_cntv_ctl(word_t val)
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MCR(CNTV_CTL, val);
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}
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#ifdef ENABLE_SMP_SUPPORT
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static inline word_t get_vmpidr(void)
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{
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word_t ret = 0;
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@ -308,7 +307,6 @@ static inline void set_vmpidr(word_t val)
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{
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MCR(VMPIDR, val);
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}
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#endif
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/** MODIFIES: phantom_machine_state */
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/** DONT_TRANSLATE */
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@ -486,10 +484,8 @@ static word_t vcpu_hw_read_reg(word_t reg_index)
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return get_cntv_off_high();
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case seL4_VCPUReg_CNTVOFFlow:
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return get_cntv_off_low();
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#ifdef ENABLE_SMP_SUPPORT
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case seL4_VCPUReg_VMPIDR:
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return get_vmpidr();
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#endif /* ENABLE_SMP_SUPPORT */
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default:
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fail("ARM/HYP: Invalid register index");
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}
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@ -123,6 +123,7 @@
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#define REG_HCR_EL2 "hcr_el2"
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#define REG_VTCR_EL2 "vtcr_el2"
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#define REG_VMPIDR_EL2 "vmpidr_el2"
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#define REG_MPIDR_EL1 "mpidr_el1"
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#define REG_ID_AA64MMFR0_EL1 "id_aa64mmfr0_el1"
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/* for EL1 SCTLR */
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@ -481,10 +482,8 @@ static word_t vcpu_hw_read_reg(word_t reg_index)
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return readCNTVOFF_EL2();
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case seL4_VCPUReg_CNTKCTL_EL1:
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return readCNTKCTL_EL1();
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#ifdef ENABLE_SMP_SUPPORT
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case seL4_VCPUReg_VMPIDR_EL2:
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return readVMPIDR_EL2();
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#endif /* ENABLE_SMP_SUPPORT */
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default:
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fail("ARM/HYP: Invalid register index");
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}
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@ -564,11 +563,9 @@ static void vcpu_hw_write_reg(word_t reg_index, word_t reg)
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case seL4_VCPUReg_CNTKCTL_EL1:
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writeCNTKCTL_EL1(reg);
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break;
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#ifdef ENABLE_SMP_SUPPORT
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case seL4_VCPUReg_VMPIDR_EL2:
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writeVMPIDR_EL2(reg);
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break;
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#endif /* ENABLE_SMP_SUPPORT */
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default:
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fail("ARM/HYP: Invalid register index");
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}
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@ -104,9 +104,7 @@ typedef enum {
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seL4_VCPUReg_R10fiq,
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seL4_VCPUReg_R11fiq,
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seL4_VCPUReg_R12fiq,
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#if CONFIG_MAX_NUM_NODES > 1
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seL4_VCPUReg_VMPIDR,
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#endif /* CONFIG_MAX_NUM_NODES > 1 */
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seL4_VCPUReg_SPSRsvc,
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seL4_VCPUReg_SPSRabt,
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seL4_VCPUReg_SPSRund,
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@ -97,10 +97,8 @@ typedef enum {
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/* thread pointer/ID registers EL0/EL1 */
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seL4_VCPUReg_TPIDR_EL1,
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#if CONFIG_MAX_NUM_NODES > 1
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/* Virtualisation Multiprocessor ID Register */
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seL4_VCPUReg_VMPIDR_EL2,
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#endif /* CONFIG_MAX_NUM_NODES > 1 */
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/* general registers x0 to x30 have been saved by traps.S */
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seL4_VCPUReg_SP_EL1,
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