manual: remove hardcoded exception registers
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Anna Lyons
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1 changed files with 4 additions and 136 deletions
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@ -105,53 +105,8 @@ The registers of a thread can be read and written with the
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\apifunc{seL4\_TCB\_ReadRegisters}{tcb_readregisters} and \apifunc{seL4\_TCB\_WriteRegisters}{tcb_writeregisters} methods.
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For some registers, the kernel will silently mask certain bits or ranges of bits off, and force them to contain certain
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values to ensure that they cannot be maliciously set to values that would compromise the running system, or to respect
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values that the architecture specifications have mandated to be certain values. On X86, these bits currently are:
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\begin{itemize}
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\item \texttt{EFLAGS}: Bits 1, 3 and 5, TF, Bits 12-31, and IF.
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\end{itemize}
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The register contents are transferred via the IPC buffer. The IPC buffer locations that registers are copied to/from are given below.
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\ifxeightsix
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\subsubsection{IA-32}
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\begin{tabularx}{\textwidth}{p{0.4\textwidth}X}
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\toprule
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\textbf{Register} & \textbf{IPC Buffer location} \\
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\midrule
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\reg{EIP} & \ipcbloc{IPCBuffer[0]} \\
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\reg{ESP} & \ipcbloc{IPCBuffer[1]} \\
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\reg{EFLAGS} & \ipcbloc{IPCBuffer[2]} \\
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\reg{EAX} & \ipcbloc{IPCBuffer[3]} \\
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\reg{EBX} & \ipcbloc{IPCBuffer[4]} \\
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\reg{ECX} & \ipcbloc{IPCBuffer[5]} \\
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\reg{EDX} & \ipcbloc{IPCBuffer[6]} \\
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\reg{ESI} & \ipcbloc{IPCBuffer[7]} \\
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\reg{EDI} & \ipcbloc{IPCBuffer[8]} \\
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\reg{EBP} & \ipcbloc{IPCBuffer[9]} \\
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\reg{TLS\_BASE} & \ipcbloc{IPCBuffer[10]} \\
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\reg{FS} & \ipcbloc{IPCBuffer[11]} \\
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\reg{GS} & \ipcbloc{IPCBuffer[12]} \\
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\bottomrule
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\end{tabularx}
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\fi
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\subsubsection{ARM}
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\begin{tabularx}{\textwidth}{p{0.4\textwidth}X}
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\toprule
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\textbf{Register} & \textbf{IPC Buffer location} \\
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\midrule
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\reg{PC} & \ipcbloc{IPCBuffer[0]} \\
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\reg{SP} & \ipcbloc{IPCBuffer[1]} \\
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\reg{CPSR} & \ipcbloc{IPCBuffer[2]} \\
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\reg{R0-R1} & \ipcbloc{IPCBuffer[3-4]} \\
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\reg{R8-R12} & \ipcbloc{IPCBuffer[5-9]} \\
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\reg{R2-R7} & \ipcbloc{IPCBuffer[10-15]} \\
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\reg{R14} & \ipcbloc{IPCBuffer[16]} \\
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\bottomrule
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\end{tabularx}
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values that the architecture specifications have mandated to be certain values.
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The register contents are transferred via the IPC buffer.
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\section{Faults}
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\label{sec:faults}
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@ -213,58 +168,10 @@ Replying to the fault IPC allows the thread to be restarted
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and/or the thread's register set to be modified. If the reply has
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a label of zero, the thread will be restarted. Additionally, if the
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message length is non-zero, the faulting thread's register set will be
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updated as shown in \autoref{tbl:unknown_syscall_result_arm} \ifxeightsix and
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\autoref{tbl:unknown_syscall_result_ia32}\fi. In this case, the number of
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updated. In this case, the number of
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registers updated is controlled with the length field of the message
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tag.
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\subsubsection{ARM}
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\begin{table}[htb]
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\begin{tabularx}{\textwidth}{XXp{0.4\textwidth}}
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\toprule
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\textbf{Value sent} & \textbf{Register set by reply} & \textbf{IPC buffer location} \\
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\midrule
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\reg{R0-R7} & (same) & \ipcbloc{seL4\_UnknownSyscall\_R[0-7]} \\
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\reg{FaultInstruction} & (same) & \ipcbloc{seL4\_UnknownSyscall\_FaultIP} \\
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\reg{SP} & (same) & \ipcbloc{seL4\_UnknownSyscall\_SP} \\
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\reg{LR} & (same) & \ipcbloc{seL4\_UnknownSyscall\_LR} \\
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\reg{CPSR} & (same) & \ipcbloc{seL4\_UknownSyscall\_CPSR} \\
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Syscall number & --- & \ipcbloc{seL4\_UnknownSyscall\_Syscall} \\
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\bottomrule
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\end{tabularx}
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\caption{\label{tbl:unknown_syscall_result_arm}Unknown system call outcome on
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the ARM architecture.}
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\end{table}
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\ifxeightsix
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\subsubsection{IA-32}
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% FIXME: This table now reflows onto the following page with the paragraph after
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% inserted here :(
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\begin{table}[htb]
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\begin{tabularx}{\textwidth}{XXp{0.4\textwidth}}
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\toprule
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\textbf{Value sent} & \textbf{Reply register} & \textbf{IPC buffer location} \\
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\midrule
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\reg{EAX} & (same) & \ipcbloc{seL4\_UnknownSyscall\_EAX} \\
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\reg{EBX} & (same) & \ipcbloc{seL4\_UnknownSyscall\_EBX} \\
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\reg{ECX} & (same) & \ipcbloc{seL4\_UnknownSyscall\_ECX} \\
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\reg{EDX} & (same) & \ipcbloc{seL4\_UnknownSyscall\_EDX} \\
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\reg{ESI} & (same) & \ipcbloc{seL4\_UnknownSyscall\_ESI} \\
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\reg{EDI} & (same) & \ipcbloc{seL4\_UnknownSyscall\_EDI} \\
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\reg{EBP} & (same) & \ipcbloc{seL4\_UnknownSyscall\_EBP} \\
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\reg{EIP} & (same) & \ipcbloc{seL4\_UnknownSyscall\_FaultIP} \\
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\reg{ESP} & (same) & \ipcbloc{seL4\_UnknownSyscall\_SP} \\
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\reg{EFLAGS} & (same) & \ipcbloc{seL4\_UnknownSyscall\_EFLAGS} \\
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Syscall number & --- & \ipcbloc{seL4\_UnknownSyscall\_Syscall} \\
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\bottomrule
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\end{tabularx}
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\caption{\label{tbl:unknown_syscall_result_ia32}Unknown system call outcome on
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the IA-32 architecture.}
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\end{table}
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\fi
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\subsection{User Exception}
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User exceptions are used to deliver architecture-defined exceptions. For
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@ -275,49 +182,10 @@ Replying to the fault IPC allows the thread to be restarted
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and/or the thread's register set to be modified. If the reply has
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a label of zero, the thread will be restarted. Additionally, if the
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message length is non-zero, the faulting thread's register set will be
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updated as shown in \autoref{tbl:user_exception_result_arm} \ifxeightsix and
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\autoref{tbl:user_exception_result_ia32}\fi. In this case, the number of
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updated. In this case, the number of
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registers updated is controlled with the length field of the message
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tag.
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\subsubsection{ARM}
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\begin{table}[htb]
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\begin{tabularx}{\textwidth}{XXp{0.4\textwidth}}
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\toprule
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\textbf{Value sent} & \textbf{Register set by reply} & \textbf{IPC buffer location} \\
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\midrule
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\reg{FaultInstruction} & (same) & \ipcbloc{seL4\_UserException\_FaultIP} \\
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\reg{SP} & (same) & \ipcbloc{seL4\_UserException\_SP} \\
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\reg{CPSR} & (same) & \ipcbloc{seL4\_UserException\_CPSR} \\
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Exception number & --- & \ipcbloc{seL4\_UserException\_Number} \\
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Exception code & --- & \ipcbloc{seL4\_UserException\_Code} \\
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\bottomrule
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\end{tabularx}
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\caption{\label{tbl:user_exception_result_arm}User exception outcome on the ARM
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architecture.}
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\end{table}
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\ifxeightsix
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\subsubsection{IA-32}
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\begin{table}[htb]
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\begin{tabularx}{\textwidth}{XXp{0.4\textwidth}}
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\toprule
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\textbf{Value sent} & \textbf{Register set by reply} & \textbf{IPC buffer location} \\
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\midrule
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\reg{EIP} & (same) & \ipcbloc{seL4\_UserException\_FaultIP} \\
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\reg{ESP} & (same) & \ipcbloc{seL4\_UserException\_SP} \\
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\reg{EFLAGS} & (same) & \ipcbloc{seL4\_UserException\_EFLAGS} \\
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Exception number & --- & \ipcbloc{seL4\_UserException\_Number} \\
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Exception code & --- & \ipcbloc{seL4\_UserException\_Code} \\
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\bottomrule
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\end{tabularx}
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\caption{\label{tbl:user_exception_result_ia32}User exception outcome on the
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IA-32 architecture.}
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\end{table}
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\fi
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\subsection{Debug Exception: Breakpoints and Watchpoints}
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\label{sec:debug_exceptions}
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