diff --git a/include/arch/arm/arch/32/mode/machine/fpu.h b/include/arch/arm/arch/32/mode/machine/fpu.h
index 19855e737..eb6c95bc5 100644
--- a/include/arch/arm/arch/32/mode/machine/fpu.h
+++ b/include/arch/arm/arch/32/mode/machine/fpu.h
@@ -24,16 +24,6 @@
 #define FPSID_SW_BIT                 23
 #define FPSID_SUBARCH_SHIFT_POS      16
 
-#define FPEXC_EX_BIT                 31
-#define FPEXC_EN_BIT                 30
-
-#if defined(CONFIG_ARM_CORTEX_A7) || defined(CONFIG_ARM_CORTEX_A9)
-#define FPEXC_DEX_BIT                29
-#endif
-
-#define FPEXC_DEX_BIT                29
-#define FPEXC_FP2V_BIT               28
-
 static void clearEnFPEXC(void)
 {
     word_t fpexc;
diff --git a/include/arch/arm/arch/32/mode/machine/registerset.h b/include/arch/arm/arch/32/mode/machine/registerset.h
index 616f64396..960e2b438 100644
--- a/include/arch/arm/arch/32/mode/machine/registerset.h
+++ b/include/arch/arm/arch/32/mode/machine/registerset.h
@@ -32,6 +32,11 @@
                              | PMODE_IDLE         \
                              | CPSR_EXTRA_FLAGS   )
 
+#define FPEXC_EX_BIT        31
+#define FPEXC_EN_BIT        30
+#define FPEXC_DEX_BIT       29
+#define FPEXC_FP2V_BIT      28
+
 /* Offsets within the user context, these need to match the order in
  * register_t below */
 #define PT_SP               (13  * 4)
@@ -245,6 +250,9 @@ void Arch_initBreakpointContext(user_context_t *context);
 static inline void Arch_initContext(user_context_t *context)
 {
     context->registers[CPSR] = CPSR_USER;
+#ifdef CONFIG_HAVE_FPU
+    context->fpuState.fpexc = BIT(FPEXC_EN_BIT);
+#endif
 #ifdef ARM_BASE_CP14_SAVE_AND_RESTORE
     Arch_initBreakpointContext(context);
 #endif