From 9100cadb511b03f93354b6a07ff1d5f1e7d338d8 Mon Sep 17 00:00:00 2001 From: Gerwin Klein Date: Fri, 24 Apr 2020 14:50:58 +0800 Subject: [PATCH] riscv: reorder setMR to align to enum Aligning the order of setMR writes to the enum order avoids having to prove that the operations commute. Signed-off-by: Gerwin Klein --- src/arch/riscv/api/faults.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/riscv/api/faults.c b/src/arch/riscv/api/faults.c index 5f95a8b18..d14b2a87c 100644 --- a/src/arch/riscv/api/faults.c +++ b/src/arch/riscv/api/faults.c @@ -33,10 +33,10 @@ word_t Arch_setMRs_fault(tcb_t *sender, tcb_t *receiver, word_t *receiveIPCBuffe switch (faultType) { case seL4_Fault_VMFault: { setMR(receiver, receiveIPCBuffer, seL4_VMFault_IP, getRestartPC(sender)); - setMR(receiver, receiveIPCBuffer, seL4_VMFault_PrefetchFault, - seL4_Fault_VMFault_get_instructionFault(sender->tcbFault)); setMR(receiver, receiveIPCBuffer, seL4_VMFault_Addr, seL4_Fault_VMFault_get_address(sender->tcbFault)); + setMR(receiver, receiveIPCBuffer, seL4_VMFault_PrefetchFault, + seL4_Fault_VMFault_get_instructionFault(sender->tcbFault)); return setMR(receiver, receiveIPCBuffer, seL4_VMFault_FSR, seL4_Fault_VMFault_get_FSR(sender->tcbFault)); }