diff --git a/include/arch/arm/arch/32/mode/machine.h b/include/arch/arm/arch/32/mode/machine.h
index eceb4ecd1..6200cd076 100644
--- a/include/arch/arm/arch/32/mode/machine.h
+++ b/include/arch/arm/arch/32/mode/machine.h
@@ -365,7 +365,7 @@ static inline void cleanByVA_PoU(vptr_t vaddr, paddr_t paddr)
     /* V6 doesn't distinguish PoU and PoC, so use the basic flush. */
     asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
 #elif defined(CONFIG_ARM_CORTEX_A7) || defined(CONFIG_ARM_CORTEX_A15) || \
-    defined(CONFIG_ARM_CORTEX_A53)
+    defined(CONFIG_ARM_CORTEX_A53) || defined(CONFIG_ARM_CORTEX_A72)
     /* Flush to coherency for table walks... Why? */
     asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
 #else
diff --git a/src/arch/arm/armv/armv8-a/32/machine_asm.S b/src/arch/arm/armv/armv8-a/32/machine_asm.S
index 671d0de81..fedcb610c 100644
--- a/src/arch/arm/armv/armv8-a/32/machine_asm.S
+++ b/src/arch/arm/armv/armv8-a/32/machine_asm.S
@@ -7,9 +7,9 @@
 #include <config.h>
 #include <machine/assembler.h>
 
-#if defined(CONFIG_ARM_CORTEX_A53)
+#if defined(CONFIG_ARM_CORTEX_A53) || defined(CONFIG_ARM_CORTEX_A72)
 
-/* A53 hardware does not support TLB locking */
+/* A53,A72 hardware does not support TLB locking */
 BEGIN_FUNC(lockTLBEntry)
     bx lr
 END_FUNC(lockTLBEntry)