From a0b4f2d25dc975f6a9198c081359c0e38e5614fb Mon Sep 17 00:00:00 2001 From: Yanfeng Liu Date: Mon, 4 May 2026 16:21:29 +0800 Subject: [PATCH] manual: Reorg riscv32/64 hardware objects This drops subsection for riscv so that subsections for rv32/64 belong to same level as those of x86 and arm32/64. Signed-off-by: Yanfeng Liu --- manual/parts/vspace.tex | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/manual/parts/vspace.tex b/manual/parts/vspace.tex index 5ccaad9f8..964dc8ac9 100644 --- a/manual/parts/vspace.tex +++ b/manual/parts/vspace.tex @@ -125,13 +125,10 @@ under a generic name. The table below shows the four-level configuration. \bottomrule \end{tabularx} -\subsection{RISC-V} - -RISC-V provides the same paging structure for all levels, \obj{PageTable}. This means the VSpace -object is here also implemented by the \obj{PageTable} object. - \subsubsection{RISC-V 32-bit} +On RISC-V, all levels use the same structure. This means VSpace is a \obj{PageTable} object. + 32-bit RISC-V \obj{PageTables} are indexed by 10 bits of virtual address. \begin{tabularx}{\textwidth}{Xlll} \toprule @@ -143,6 +140,8 @@ object is here also implemented by the \obj{PageTable} object. \subsubsection{RISC-V 64-bit} +On RISC-V, all levels use the same structure. This means VSpace is a \obj{PageTable} object. + 64-bit RISC-V follows the SV39 model, where \obj{PageTables} are indexed by 9 bits of virtual address. Although RISC-V allows for multiple different numbers of paging levels, currently seL4 only supports exactly three levels