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gic_v3: fix offset for gicd iroutern mem-map reg

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GICD_IROUTERn is at the offset 0x6100 for SPI 32.
SGIs and PPIs do not have a target since they are private to CPUs.
Signed-off-by: JorgeMVP <jorgepereira89@gmail.com>
This commit is contained in:
JorgeMVP 2023-04-06 21:27:35 +02:00 committed by Kent McLeod
parent fb808f0528
commit a7845d297d
2 changed files with 5 additions and 3 deletions
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4
include/arch/arm/arch/machine/gic_v3.h
View file

@ -170,7 +170,9 @@ struct gic_dist_map {
uint32_t spendsgirn[4]; /* [0xF20, 0xF30) */
uint32_t res9[5236]; /* [0x0F30, 0x6100) */
uint64_t iroutern[960]; /* [0x6100, 0x7F00) */
uint64_t iroutern[960]; /* [0x6100, 0x7F00) irouter<n> to configure IRQs
* with INTID from 32 to 1019. iroutern[0] is the
* interrupt routing for SPI 32 */
};
_Static_assert(0x6100 == SEL4_OFFSETOF(struct gic_dist_map, iroutern),

4
src/arch/arm/machine/gic_v3.c
View file

@ -173,7 +173,7 @@ BOOT_CODE static void dist_init(void)
/* Route all global IRQs to this CPU */
affinity = mpidr_to_gic_affinity();
for (i = SPI_START; i < nr_lines; i++) {
gic_dist->iroutern[i] = affinity;
gic_dist->iroutern[i - SPI_START] = affinity;
}
}
@ -381,7 +381,7 @@ void setIRQTarget(irq_t irq, seL4_Word target)
}
word_t hw_irq = IRQT_TO_IRQ(irq);
gic_dist->iroutern[hw_irq] = MPIDR_AFF_MASK(mpidr_map[target]);
gic_dist->iroutern[hw_irq - SPI_START] = MPIDR_AFF_MASK(mpidr_map[target]);
}
#endif /* ENABLE_SMP_SUPPORT */