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risc-v: fix register bug

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An aditional parameter for the dtb was added to the init_kernel
function call in the elfloader. The corresponding _start entry
in the kernel was never updated.

Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
This commit is contained in:
Oliver Scott 2021-05-14 15:46:35 +10:00 committed by Oliver Scott
parent 2f35873885
commit baad619db3
1 changed files with 3 additions and 3 deletions
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6
src/arch/riscv/head.S
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@ -17,8 +17,8 @@
.extern trap_entry
/*
* When SMP is enabled, the elfloader passes the hart ID in a4
* and logical core ID in a5.
* When SMP is enabled, the elfloader passes the hart ID in a6
* and logical core ID in a7.
*/
_start:
fence.i
@ -32,7 +32,7 @@ _start:
#if CONFIG_MAX_NUM_NODES > 1
/* setup the per-core stack */
mv t0, a5
mv t0, a7
slli t0, t0, CONFIG_KERNEL_STACK_BITS
add sp, sp, t0
/* put the stack in sscratch */