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ARM, GICv3: Fix GICD_CTLR_ARE_NS

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See issue #1489.

Signed-off-by: Indan Zupancic <indan@nul.nu>
This commit is contained in:
Indan Zupancic 2025-07-02 11:45:11 +01:00
parent 6dbe58ef0c
commit bcf5ab7924
1 changed files with 3 additions and 2 deletions
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5
include/arch/arm/arch/machine/gic_v3.h
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@ -32,9 +32,10 @@
/* Register bits */
#define GICD_CTLR_RWP BIT(31)
#define GICD_CTLR_ARE_NS BIT(4)
#define GICD_CTLR_ENABLE_G1NS BIT(1)
#define GICD_CTLR_ARE_NS BIT(5)
#define GICD_CTLR_ENABLE_G1NS BIT(1)
#define GICD_CTLR_ENABLE_G0 BIT(0)
#define GICD_IROUTER_SPI_MODE_ANY BIT(31)
#define GICD_TYPE_LINESNR 0x01f