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arm: Added define for VMPIDR and VMPIDR_EL2

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Added constant definitions for the VMPIDR (arm32) and VMPIDR_EL2
(arm64) registers. These being vcpu registers that can be
written, read, saved and restored. The 'Virtualization Multiprocessor
ID Register' (VMPIDR) is needed to program a vcpu's affinity during
initialisation. This is currently only exposed on SMP configurations.

Co-authored-by: Anna Lyons <anna@gh.st>
This commit is contained in:
Alison Felizzi 2020-01-28 17:08:17 +11:00 committed by Kent McLeod
parent 91f8ff706c
commit bddd405417
5 changed files with 53 additions and 0 deletions
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1
include/arch/arm/arch/32/mode/machine.h
View file

@ -63,6 +63,7 @@
#define ID_DFR0 " p15, 0, %0, c0, c1, 2" /* 32-bit RO Debug feature register */
#define ID_PFR1 " p15, 0, %0, c0, c1, 1" /* 32-bit RO CPU feature register */
#define CPACR " p15, 0, %0, c1, c0, 2" /* 32-bit Architectural Feature Access Control Register */
#define VMPIDR " p15, 4, %0, c0, c0, 5" /* 32-bit RW Virtualization Multiprocessor ID Register */
/* Use Hypervisor Physical timer */
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT

23
include/arch/arm/armv/armv7-a/armv/vcpu.h
View file

@ -303,6 +303,20 @@ static inline void set_cntv_ctl(word_t val)
MCR(CNTV_CTL, val);
}
#ifdef ENABLE_SMP_SUPPORT
static inline word_t get_vmpidr(void)
{
word_t ret = 0;
MRC(VMPIDR, ret);
return ret;
}
static inline void set_vmpidr(word_t val)
{
MCR(VMPIDR, val);
}
#endif
/** MODIFIES: phantom_machine_state */
/** DONT_TRANSLATE */
static inline void set_cntv_cval_64(uint64_t val)
@ -481,6 +495,10 @@ static word_t vcpu_hw_read_reg(word_t reg_index)
return get_cntv_off_high();
case seL4_VCPUReg_CNTVOFFlow:
return get_cntv_off_low();
#ifdef ENABLE_SMP_SUPPORT
case seL4_VCPUReg_VMPIDR:
return get_vmpidr();
#endif /* ENABLE_SMP_SUPPORT */
default:
fail("ARM/HYP: Invalid register index");
}
@ -617,6 +635,11 @@ static void vcpu_hw_write_reg(word_t reg_index, word_t reg)
case seL4_VCPUReg_CNTVOFFlow:
set_cntv_off_low(reg);
break;
#ifdef ENABLE_SMP_SUPPORT
case seL4_VCPUReg_VMPIDR:
set_vmpidr(reg);
break;
#endif /* ENABLE_SMP_SUPPORT */
default:
fail("ARM/HYP: Invalid register index");
}

21
include/arch/arm/armv/armv8-a/64/armv/vcpu.h
View file

@ -122,6 +122,7 @@
#define REG_CNTVOFF_EL2 "cntvoff_el2"
#define REG_HCR_EL2 "hcr_el2"
#define REG_VTCR_EL2 "vtcr_el2"
#define REG_VMPIDR_EL2 "vmpidr_el2"
#define REG_ID_AA64MMFR0_EL1 "id_aa64mmfr0_el1"
/* for EL1 SCTLR */
@ -383,6 +384,18 @@ static inline void writeCNTVOFF_EL2(word_t reg)
MSR(REG_CNTVOFF_EL2, reg);
}
static inline word_t readVMPIDR_EL2(void)
{
word_t reg;
MRS(REG_VMPIDR_EL2, reg);
return reg;
}
static inline void writeVMPIDR_EL2(word_t reg)
{
MSR(REG_VMPIDR_EL2, reg);
}
static word_t vcpu_hw_read_reg(word_t reg_index)
{
word_t reg = 0;
@ -431,6 +444,10 @@ static word_t vcpu_hw_read_reg(word_t reg_index)
return readCNTV_CVAL_EL0();
case seL4_VCPUReg_CNTVOFF:
return readCNTVOFF_EL2();
#ifdef ENABLE_SMP_SUPPORT
case seL4_VCPUReg_VMPIDR_EL2:
return readVMPIDR_EL2();
#endif /* ENABLE_SMP_SUPPORT */
default:
fail("ARM/HYP: Invalid register index");
}
@ -486,6 +503,10 @@ static void vcpu_hw_write_reg(word_t reg_index, word_t reg)
return writeCNTV_CVAL_EL0(reg);
case seL4_VCPUReg_CNTVOFF:
return writeCNTVOFF_EL2(reg);
#ifdef ENABLE_SMP_SUPPORT
case seL4_VCPUReg_VMPIDR_EL2:
return writeVMPIDR_EL2(reg);
#endif /* ENABLE_SMP_SUPPORT */
default:
fail("ARM/HYP: Invalid register index");
}

3
libsel4/sel4_arch_include/aarch32/sel4/sel4_arch/constants.h
View file

@ -118,6 +118,9 @@ enum {
seL4_VCPUReg_R10fiq,
seL4_VCPUReg_R11fiq,
seL4_VCPUReg_R12fiq,
#if CONFIG_MAX_NUM_NODES > 1
seL4_VCPUReg_VMPIDR,
#endif /* CONFIG_MAX_NUM_NODES > 1 */
seL4_VCPUReg_SPSRsvc,
seL4_VCPUReg_SPSRabt,
seL4_VCPUReg_SPSRund,

5
libsel4/sel4_arch_include/aarch64/sel4/sel4_arch/constants.h
View file

@ -105,6 +105,11 @@ enum {
/* thread pointer/ID registers EL0/EL1 */
seL4_VCPUReg_TPIDR_EL1,
#if CONFIG_MAX_NUM_NODES > 1
/* Virtualisation Multiprocessor ID Register */
seL4_VCPUReg_VMPIDR_EL2,
#endif /* CONFIG_MAX_NUM_NODES > 1 */
/* general registers x0 to x30 have been saved by traps.S */
seL4_VCPUReg_SP_EL1,
seL4_VCPUReg_ELR_EL1,