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trivial: style and comment

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Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
This commit is contained in:
Oliver Scott 2020-08-04 13:37:36 +10:00
parent 935714a4cb
commit c66d9cee7a
12 changed files with 855 additions and 827 deletions
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2
configs/seL4Config.cmake
View file

@ -125,8 +125,10 @@ unset(CONFIGURE_CLK_SHIFT CACHE)
unset(CONFIGURE_CLK_MAGIC CACHE)
unset(CONFIGURE_KERNEL_WCET CACHE)
unset(CONFIGURE_TIMER_PRECISION CACHE)
# CONFIGURE_MAX_CB and CONFIGURE_MAX_SID are related to the kernel SMMU on Arm.
unset(CONFIGURE_MAX_SID CACHE)
unset(CONFIGURE_MAX_CB CACHE)
# CLK_SHIFT and CLK_MAGIC are generated from tools/reciprocal.py
# based on the TIMER_CLK_HZ to simulate division.
# This could be moved to a cmake function

6
src/arch/arm/64/kernel/vspace.c
View file

@ -1218,8 +1218,9 @@ static inline void invalidateTLBByASID(asid_t asid)
{
#ifdef CONFIG_ARM_SMMU
vspace_root_t bind_cb = getASIDBindCB(asid);
if (unlikely(vtable_invalid_get_bind_cb(bind_cb)))
if (unlikely(vtable_invalid_get_bind_cb(bind_cb))) {
invalidateSMMUTLBByASID(asid, vtable_invalid_get_bind_cb(bind_cb));
}
#endif
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
vspace_root_t stored_hw_asid;
@ -1238,8 +1239,9 @@ static inline void invalidateTLBByASIDVA(asid_t asid, vptr_t vaddr)
{
#ifdef CONFIG_ARM_SMMU
vspace_root_t bind_cb = getASIDBindCB(asid);
if (unlikely(vtable_invalid_get_bind_cb(bind_cb)))
if (unlikely(vtable_invalid_get_bind_cb(bind_cb))) {
invalidateSMMUTLBByASIDVA(asid, vaddr, vtable_invalid_get_bind_cb(bind_cb));
}
#endif
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
vspace_root_t stored_hw_asid;

6
src/arch/arm/64/object/objecttype.c
View file

@ -412,7 +412,7 @@ cap_t Arch_createObject(object_t t, void *regionBase, word_t userSize, bool_t de
);
#ifndef AARCH64_VSPACE_S2_START_L1
case seL4_ARM_PageGlobalDirectoryObject:
#ifdef CONFIG_ARM_SMMU
#ifdef CONFIG_ARM_SMMU
return cap_page_global_directory_cap_new(
asidInvalid, /* capPGDMappedASID */
@ -420,14 +420,14 @@ cap_t Arch_createObject(object_t t, void *regionBase, word_t userSize, bool_t de
0, /* capPGDIsMapped */
CB_INVALID /* capPGDMappedCB */
);
#else
#else
return cap_page_global_directory_cap_new(
asidInvalid, /* capPGDMappedASID */
(word_t)regionBase, /* capPGDBasePtr */
0 /* capPGDIsMapped */
);
#endif /*!CONFIG_ARM_SMMU*/
#endif /*!CONFIG_ARM_SMMU*/
#endif /*!AARCH64_VSPACE_S2_START_L1*/
case seL4_ARM_PageUpperDirectoryObject:
return cap_page_upper_directory_cap_new(

6
src/arch/arm/config.cmake
View file

@ -113,11 +113,7 @@ config_option(
DEFAULT_DISABLED OFF
)
config_option(
KernelArmSMMU ARM_SMMU "Enable SystemMMU"
DEFAULT OFF
DEPENDS "KernelPlatformTx2"
)
config_option(KernelArmSMMU ARM_SMMU "Enable SystemMMU" DEFAULT OFF DEPENDS "KernelPlatformTx2")
config_option(
KernelTk1SMMU TK1_SMMU "Enable SystemMMU for the Tegra TK1 SoC"

3
src/arch/arm/kernel/boot.c
View file

@ -125,7 +125,8 @@ BOOT_CODE static void init_irqs(cap_t root_cnode_cap)
}
#ifdef CONFIG_ARM_SMMU
BOOT_CODE static void init_smmu (cap_t root_cnode_cap) {
BOOT_CODE static void init_smmu(cap_t root_cnode_cap)
{
plat_smmu_init();
/*provide the SID and CB control cap*/
write_slot(SLOT_PTR(pptr_of_cap(root_cnode_cap), seL4_CapSMMUSIDControl), cap_sid_control_cap_new());

12
src/arch/arm/object/smmu.c
View file

@ -20,7 +20,8 @@ static exception_t checkARMCBVspace(cap_t cap)
exception_t decodeARMSIDControlInvocation(word_t label, unsigned int length, cptr_t cptr,
cte_t *srcSlot, cap_t cap, extra_caps_t extraCaps,
bool_t call, word_t *buffer) {
bool_t call, word_t *buffer)
{
word_t index, depth, sid;
cte_t *destSlot;
@ -95,7 +96,8 @@ exception_t decodeARMSIDControlInvocation(word_t label, unsigned int length, cpt
exception_t decodeARMSIDInvocation(word_t label, unsigned int length, cptr_t cptr,
cte_t *srcSlot, cap_t cap, extra_caps_t extraCaps,
bool_t call, word_t *buffer) {
bool_t call, word_t *buffer)
{
cap_t cbCap;
cte_t *cbCapSlot;
cte_t *cbAssignSlot;
@ -181,7 +183,8 @@ exception_t smmu_delete_sid(cap_t cap)
exception_t decodeARMCBControlInvocation(word_t label, unsigned int length, cptr_t cptr,
cte_t *srcSlot, cap_t cap, extra_caps_t extraCaps,
bool_t call, word_t *buffer) {
bool_t call, word_t *buffer)
{
word_t index, depth, cb;
cte_t *destSlot;
@ -245,7 +248,8 @@ exception_t decodeARMCBControlInvocation(word_t label, unsigned int length, cptr
exception_t decodeARMCBInvocation(word_t label, unsigned int length, cptr_t cptr,
cte_t *srcSlot, cap_t cap, extra_caps_t extraCaps,
bool_t call, word_t *buffer) {
bool_t call, word_t *buffer)
{
cap_t vspaceCap;
cte_t *vspaceCapSlot;

6
src/drivers/smmu/config.cmake
View file

@ -6,8 +6,4 @@
cmake_minimum_required(VERSION 3.7.2)
register_driver(
compatibility_strings "arm,mmu-500"
PREFIX src/drivers/smmu
CFILES "smmuv2.c"
)
register_driver(compatibility_strings "arm,mmu-500" PREFIX src/drivers/smmu CFILES "smmuv2.c")

102
src/drivers/smmu/smmuv2.c
View file

@ -56,22 +56,22 @@ static struct smmu_table_config smmu_stage_table_config;
static inline uint32_t smmu_read_reg32(pptr_t base, uint32_t index)
{
return *(volatile uint32_t*)(base + index);
return *(volatile uint32_t *)(base + index);
}
static inline void smmu_write_reg32(pptr_t base, uint32_t index, uint32_t val)
{
*(volatile uint32_t*) (base + index) = val;
*(volatile uint32_t *)(base + index) = val;
}
static inline uint64_t smmu_read_reg64(pptr_t base, uint32_t index)
{
return *(volatile uint64_t*) (base + index);
return *(volatile uint64_t *)(base + index);
}
static inline void smmu_write_reg64(pptr_t base, uint32_t index, uint64_t val)
{
*(volatile uint64_t *) (base + index) = val;
*(volatile uint64_t *)(base + index) = val;
}
static void smmu_tlb_sync(pptr_t base, uint32_t sync, uint32_t status)
@ -80,13 +80,15 @@ static void smmu_tlb_sync(pptr_t base, uint32_t sync, uint32_t status)
smmu_write_reg32(base, sync, SMMU_TLB_SYNC_MASK);
while (count < TLBSYNC_LOOP) {
/*pulling the active flag, reading the TLB command state.*/
if (!(smmu_read_reg32(base, status) & TLBSTATUS_GSACTIVE))
if (!(smmu_read_reg32(base, status) & TLBSTATUS_GSACTIVE)) {
break;
}
count++;
}
}
static inline uint32_t smmu_obs_size_to_bits(uint32_t size) {
static inline uint32_t smmu_obs_size_to_bits(uint32_t size)
{
/*coverting the output bus address size into address bit, defined in
IDx registers*/
switch (size) {
@ -105,7 +107,8 @@ static inline uint32_t smmu_obs_size_to_bits(uint32_t size) {
return 48;
}
}
static inline uint32_t smmu_ubs_size_to_bits(uint32_t size) {
static inline uint32_t smmu_ubs_size_to_bits(uint32_t size)
{
/*coverting the upstream address size into address bit, defined in
IDx registers*/
switch (size) {
@ -180,18 +183,23 @@ BOOT_CODE static void smmu_config_prob(void)
/*ID0*/
reg = smmu_read_reg32(SMMU_GR0_PPTR, SMMU_IDR0);
/*stages supported*/
if (reg & IDR0_S1TS)
if (reg & IDR0_S1TS) {
smmu_dev_knowledge.supported_trans |= STAGE1_TRANS;
if (reg & IDR0_S2TS)
}
if (reg & IDR0_S2TS) {
smmu_dev_knowledge.supported_trans |= STAGE2_TRANS;
if (reg & IDR0_NTS)
}
if (reg & IDR0_NTS) {
smmu_dev_knowledge.supported_trans |= NESTED_TRANS;
}
/*stream matching register*/
if (reg & IDR0_SMS)
if (reg & IDR0_SMS) {
smmu_dev_knowledge.stream_match = true;
}
/*address translation operation*/
if ((reg & IDR0_ATOSNS) == 0)
if ((reg & IDR0_ATOSNS) == 0) {
smmu_dev_knowledge.trans_op = true;
}
/*AARCH32 translation format support*/
field = IDR0_PTFS_VAL(reg & IDR0_PTFS);
if (field == PTFS_AARCH32S_AARCH32L) {
@ -207,11 +215,13 @@ BOOT_CODE static void smmu_config_prob(void)
* hence no requirement to specify implemented interrupts here.*/
smmu_dev_knowledge.num_cfault_ints = IDR0_NUMIRPT_VAL(reg & IDR0_NUMIRPT);
/*coherent translation table walk*/
if (reg & IDR0_CTTW)
if (reg & IDR0_CTTW) {
smmu_dev_knowledge.cotable_walk = true;
}
/*broadcast TLB maintenance*/
if (reg & IDR0_BTM)
if (reg & IDR0_BTM) {
smmu_dev_knowledge.broadcast_tlb = true;
}
/*number of stream IDs*/
smmu_dev_knowledge.num_stream_ids = (1 << IDR0_NUMSIDB_VAL(reg & IDR0_NUMSIDB)) - 1;
/*number of stream mapping register groups*/
@ -220,10 +230,11 @@ BOOT_CODE static void smmu_config_prob(void)
/*ID1*/
reg = smmu_read_reg32(SMMU_GR0_PPTR, SMMU_IDR1);
/*smmu page size*/
if (reg & IDR1_PAGESIZE )
if (reg & IDR1_PAGESIZE) {
smmu_dev_knowledge.smmu_page_size = SMMU_PAGE_64KB;
else
} else {
smmu_dev_knowledge.smmu_page_size = SMMU_PAGE_4KB;
}
/*smmu num pages, 2^(numdxb + 1)*/
field = IDR1_NUMPAGENDXB_VAL(reg & IDR1_NUMPAGENDXB);
smmu_dev_knowledge.smmu_num_pages = 1 << (field + 1);
@ -238,18 +249,22 @@ BOOT_CODE static void smmu_config_prob(void)
/*ID2*/
reg = smmu_read_reg32(SMMU_GR0_PPTR, SMMU_IDR2);
/*VNID16S*/
if (reg & IDR2_VMID16S)
if (reg & IDR2_VMID16S) {
smmu_dev_knowledge.vmid16 = true;
}
/*PTFSV8_64KB*/
if (reg & IDR2_PTFSV8_64)
if (reg & IDR2_PTFSV8_64) {
smmu_dev_knowledge.supported_fmt |= TRANS_PAGES_64KB;
}
/*PTFSV8_16KB*/
if (reg & IDR2_PTFSV8_16)
if (reg & IDR2_PTFSV8_16) {
smmu_dev_knowledge.supported_fmt |= TRANS_PAGES_16KB;
}
/*PTFSV8_64KB*/
if (reg & IDR2_PTFSV8_4)
if (reg & IDR2_PTFSV8_4) {
smmu_dev_knowledge.supported_fmt |= TRANS_PAGES_4KB;
}
/*UBS virtual address size*/
smmu_dev_knowledge.va_bits = smmu_ubs_size_to_bits(IDR2_UBS_VAL(reg & IDR2_UBS));
/*OAS*/
@ -280,17 +295,20 @@ BOOT_CODE static void smmu_dev_reset(void)
/*the number of stream-to-context is realted to the stream indexing method*/
if (smmu_dev_knowledge.stream_match) {
/*stream matching*/
for (int i = 0; i < smmu_dev_knowledge.num_stream_map_groups; i++)
for (int i = 0; i < smmu_dev_knowledge.num_stream_map_groups; i++) {
smmu_write_reg32(SMMU_GR0_PPTR, SMMU_S2CRn(i), reg);
}
/*reset the stream match registers as invalid*/
reg = SMR_VALID_SET(SMR_VALID_DIS);
for (int i = 0; i < smmu_dev_knowledge.num_stream_map_groups; i++)
for (int i = 0; i < smmu_dev_knowledge.num_stream_map_groups; i++) {
smmu_write_reg32(SMMU_GR0_PPTR, SMMU_SMRn(i), reg);
}
} else {
/*stream ID*/
for (int i = 0; i < smmu_dev_knowledge.num_stream_ids; i++)
for (int i = 0; i < smmu_dev_knowledge.num_stream_ids; i++) {
smmu_write_reg32(SMMU_GR0_PPTR, SMMU_S2CRn(i), reg);
}
}
/*special init requested by the smmu-500: start*/
reg = smmu_read_reg32(SMMU_GR0_PPTR, SMMU_IDR7);
@ -299,8 +317,9 @@ BOOT_CODE static void smmu_dev_reset(void)
reg = smmu_read_reg32(SMMU_GR0_PPTR, SMMU_sACR);
/*unlock the write access to SMMU_CBn_ACTLR,
only provided in version 2 and above*/
if (major >= 2)
if (major >= 2) {
reg &= ~ACR_CACHE_LOCK;
}
/*enable the TLB to cache bypassing*/
reg |= ACR_S2CRB_TLBEN | ACR_SMTNMB_TLBEN;
smmu_write_reg32(SMMU_GR0_PPTR, SMMU_sACR, reg);
@ -357,8 +376,9 @@ BOOT_CODE void plat_smmu_init(void)
}
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
static void smmu_config_stage2 (struct smmu_table_config *cfg,
vspace_root_t *vspace) {
static void smmu_config_stage2(struct smmu_table_config *cfg,
vspace_root_t *vspace)
{
uint32_t reg = 0;
/*SMMU_CBn_TCR*/
reg |= CBn_TCR_SH0_SET(CBn_TCR_SH_INNER);
@ -382,9 +402,10 @@ static void smmu_config_stage2 (struct smmu_table_config *cfg,
cfg->ttbr[0] = ttbr_new(0, pptr_to_paddr(vspace)).words[0];
}
#else
static void smmu_config_stage1 (struct smmu_table_config *cfg,
static void smmu_config_stage1(struct smmu_table_config *cfg,
bool_t coherence, uint32_t pa_bits,
vspace_root_t *vspace, asid_t asid) {
vspace_root_t *vspace, asid_t asid)
{
uint32_t reg = 0;
/*SMMU_CBn_TCR*/
if (coherence) {
@ -446,7 +467,8 @@ static void smmu_config_stage1 (struct smmu_table_config *cfg,
#endif /*CONFIG_ARM_HYPERVISOR_SUPPORT*/
void smmu_cb_assign_vspace(word_t cb, vspace_root_t *vspace, asid_t asid) {
void smmu_cb_assign_vspace(word_t cb, vspace_root_t *vspace, asid_t asid)
{
uint32_t reg = 0;
uint32_t vmid = cb;
/* For the stage 2 translation, the VMID space is designed as a private
@ -468,8 +490,9 @@ void smmu_cb_assign_vspace(word_t cb, vspace_root_t *vspace, asid_t asid) {
/*CBA2R*/
/*currently only support aarch64*/
reg = CBA2Rn_VA64_SET;
if (smmu_dev_knowledge.vmid16)
if (smmu_dev_knowledge.vmid16) {
reg |= CBA2Rn_VMID_SET(vmid);
}
smmu_write_reg32(SMMU_GR1_PPTR, SMMU_CBA2Rn(cb), reg);
/*CBAR*/
@ -477,8 +500,9 @@ void smmu_cb_assign_vspace(word_t cb, vspace_root_t *vspace, asid_t asid) {
/*stage 2 translation only, CBAR_TYPE_S2_TRANS*/
reg = CBARn_TYPE_SET(CBARn_TYPE_STAGE2);
/*8 bit VMID*/
if (!smmu_dev_knowledge.vmid16)
if (!smmu_dev_knowledge.vmid16) {
reg |= CBARn_VMID_SET(vmid);
}
#else
/*stage 1 translation only, CBAR_TYPE_S1_TRANS_S2_BYPASS*/
reg = CBARn_TYPE_SET(CBARn_TYPE_STAGE1);
@ -510,7 +534,8 @@ void smmu_cb_assign_vspace(word_t cb, vspace_root_t *vspace, asid_t asid) {
smmu_write_reg32(SMMU_CBn_BASE_PPTR(cb), SMMU_CBn_SCTLR, reg);
}
void smmu_cb_disable(word_t cb, asid_t asid) {
void smmu_cb_disable(word_t cb, asid_t asid)
{
uint32_t reg = smmu_read_reg32(SMMU_CBn_BASE_PPTR(cb), SMMU_CBn_SCTLR);
reg &= ~CBn_SCTLR_M;
@ -518,7 +543,8 @@ void smmu_cb_disable(word_t cb, asid_t asid) {
smmu_tlb_invalidate_cb(cb, asid);
}
void smmu_sid_bind_cb(word_t sid, word_t cb) {
void smmu_sid_bind_cb(word_t sid, word_t cb)
{
uint32_t reg = 0;
reg = S2CR_PRIVCFG_SET(S2CR_PRIVCFG_DEFAULT);
@ -545,7 +571,8 @@ void smmu_sid_unbind(word_t sid)
}
}
void smmu_tlb_invalidate_all(void) {
void smmu_tlb_invalidate_all(void)
{
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
/*on hyp entries*/
smmu_write_reg32(SMMU_GR0_PPTR, SMMU_TLBIALLH, SMMU_TLB_INVALL_MASK);
@ -557,7 +584,8 @@ void smmu_tlb_invalidate_all(void) {
smmu_tlb_sync(SMMU_GR0_PPTR, SMMU_sTLBGSYNC, SMMU_sTLBGSTATUS);
}
void smmu_tlb_invalidate_cb(int cb, asid_t asid) {
void smmu_tlb_invalidate_cb(int cb, asid_t asid)
{
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
/*stage 2*/
/* SMMU uses a private VMID space. Each context bank assigns its VMID with its
@ -575,7 +603,7 @@ void smmu_tlb_invalidate_cb(int cb, asid_t asid) {
void smmu_tlb_invalidate_cb_va(int cb, asid_t asid, vptr_t vaddr)
{
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
/*stage 2*/
/* invalidate all unlocated TLB entries in the stage 2 translation
* associated with the given IPA*/
@ -606,7 +634,7 @@ void smmu_clear_fault_state(void)
void smmu_cb_read_fault_state(int cb, uint32_t *status, word_t *address)
{
*status = smmu_read_reg32(SMMU_CBn_BASE_PPTR(cb), SMMU_CBn_FSR);
*address = smmu_read_reg64(SMMU_CBn_BASE_PPTR(cb),SMMU_CBn_FAR);
*address = smmu_read_reg64(SMMU_CBn_BASE_PPTR(cb), SMMU_CBn_FAR);
}
void smmu_cb_clear_fault_state(int cb)

3
src/plat/tx2/config.cmake
View file

@ -27,8 +27,7 @@ if(KernelPlatformTx2)
TIMER drivers/timer/arm_generic.h
CLK_SHIFT 57u
CLK_MAGIC 4611686019u
KERNEL_WCET 10u
SMMU drivers/smmu/smmuv2.h
KERNEL_WCET 10u SMMU drivers/smmu/smmuv2.h
MAX_SID 128
MAX_CB 64
)