RISC-V: Add PLIC interface and HiFive driver
We assume the PLIC is currently the only global interrupt controller that RISC-V platforms are going to use. Each platform may have a different programmers model for interracting with the hardware controller. We provide a common interface for PLIC drivers to implement that the kernel will use to manage IRQs. Also authored by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>
This commit is contained in:
Kent McLeod
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4b24006678
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c73d5178d9
4 changed files with 185 additions and 7 deletions
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@ -13,6 +13,114 @@
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#ifndef __PLAT_INSTANCE_HARDWARE_H
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#define __PLAT_INSTANCE_HARDWARE_H
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#define PLIC_MAX_NUM_INT 53
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#define PLIC_BASE 0x0C000000
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#define PLIC_PPTR_BASE 0xFFFFFFFFCC000000
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#define PLIC_HARTID 2
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#define PLIC_PRIO 0x0
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#define PLIC_PRIO_PER_ID 0x4
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#define PLIC_EN 0x2000
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#define PLIC_EN_PER_HART 0x80
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#define PLIC_THRES 0x200000
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#define PLIC_THRES_PER_HART 0x1000
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#define PLIC_THRES_CLAIM 0x4
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static inline uint32_t readl(const volatile uint64_t addr)
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{
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uint32_t val;
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asm volatile("lw %0, 0(%1)" : "=r"(val) : "r"(addr));
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return val;
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}
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static inline void writel(uint32_t val, volatile uint64_t addr)
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{
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asm volatile("sw %0, 0(%1)" : : "r"(val), "r"(addr));
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}
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static inline interrupt_t plic_get_claim(void)
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{
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/* Read the claim register for our HART interrupt context */
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return readl(PLIC_PPTR_BASE + PLIC_THRES + PLIC_THRES_PER_HART * PLIC_HARTID +
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PLIC_THRES_CLAIM);
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}
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static inline void plic_complete_claim(interrupt_t irq)
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{
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/* Complete the IRQ claim by writing back to the claim register. */
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writel(irq, PLIC_PPTR_BASE + PLIC_THRES + PLIC_THRES_PER_HART * PLIC_HARTID +
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PLIC_THRES_CLAIM);
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}
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static inline void plic_mask_irq(bool_t disable, interrupt_t irq)
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{
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uint64_t addr = 0;
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uint32_t val = 0;
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if (irq >= 32) {
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irq -= 32;
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addr = 0x4;
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}
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addr += PLIC_PPTR_BASE + PLIC_EN;
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val = readl(addr + PLIC_EN_PER_HART * PLIC_HARTID);
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if (disable) {
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val &= ~BIT(irq);
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} else {
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val |= BIT(irq);
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}
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writel(val, addr + PLIC_EN_PER_HART * PLIC_HARTID);
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if (!disable) {
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/* Clear any pending claims if we are enabling otherwise they may not
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* be raised again */
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plic_complete_claim(irq);
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}
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}
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static inline void plic_init_controller(void)
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{
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uint32_t pending;
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/* Clear all pending bits */
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pending = readl(PLIC_PPTR_BASE + 0x1000);
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for (int i = 0; i < 32 ; i++) {
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if (pending & (1 << i)) {
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readl(PLIC_PPTR_BASE + PLIC_THRES +
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PLIC_THRES_PER_HART * PLIC_HARTID +
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PLIC_THRES_CLAIM);
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}
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}
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pending = readl(PLIC_PPTR_BASE + 0x1004);
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for (int i = 0; i < 22 ; i++) {
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if (pending & (1 << i)) {
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readl(PLIC_PPTR_BASE + PLIC_THRES +
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PLIC_THRES_PER_HART * PLIC_HARTID +
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PLIC_THRES_CLAIM);
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}
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}
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/* Disable interrupts */
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writel(0, PLIC_PPTR_BASE + PLIC_EN + PLIC_EN_PER_HART * PLIC_HARTID);
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writel(0, PLIC_PPTR_BASE + PLIC_EN + PLIC_EN_PER_HART * PLIC_HARTID + 0x4);
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/* Set threshold to zero */
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writel(1, (PLIC_PPTR_BASE + PLIC_THRES + PLIC_THRES_PER_HART * PLIC_HARTID));
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/* Set the priorities of all interrupts to 1 */
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for (int i = 1; i <= PLIC_MAX_NUM_INT + 1; i++) {
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writel(2, PLIC_PPTR_BASE + PLIC_PRIO + PLIC_PRIO_PER_ID * i);
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}
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}
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/* Available physical memory regions on platform (RAM minus kernel image). */
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/* NOTE: Regions are not allowed to be adjacent! */
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static p_region_t BOOT_DATA avail_p_regs[] = {
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@ -13,6 +13,25 @@
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#ifndef __PLAT_INSTANCE_HARDWARE_H
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#define __PLAT_INSTANCE_HARDWARE_H
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#define PLIC_MAX_NUM_INT 0
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static inline interrupt_t plic_get_claim(void)
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{
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return irqInvalid;
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}
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static inline void plic_complete_claim(interrupt_t irq)
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{
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}
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static inline void plic_mask_irq(bool_t disable, interrupt_t irq)
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{
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}
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static inline void plic_init_controller(void)
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{
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}
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/* Available physical memory regions on platform (RAM minus kernel image). */
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/* NOTE: Regions are not allowed to be adjacent! */
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static p_region_t BOOT_DATA avail_p_regs[] = {
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@ -13,6 +13,26 @@
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#ifndef __PLAT_INSTANCE_HARDWARE_H
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#define __PLAT_INSTANCE_HARDWARE_H
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#define PLIC_MAX_NUM_INT 0
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static inline interrupt_t plic_get_claim(void)
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{
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return irqInvalid;
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}
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static inline void plic_complete_claim(interrupt_t irq)
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{
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}
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static inline void plic_mask_irq(bool_t disable, interrupt_t irq)
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{
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}
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static inline void plic_init_controller(void)
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{
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}
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/* Available physical memory regions on platform (RAM minus kernel image). */
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/* NOTE: Regions are not allowed to be adjacent! */
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static p_region_t BOOT_DATA avail_p_regs[] = {
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@ -21,6 +21,44 @@
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#ifndef __ASSEMBLER__
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/*
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* RISC-V defines a Platform-level interrupt controller (PLIC) (priv-1.10).
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* It is responsible for managing global interrupts in a RISC-V system.
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*
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* A PLIC takes multiple interrupt sources from external devices and delivers
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* them to different HART contexts depending on per IRQ configuration registers.
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* A HART context is a given privilege level on a given HART. If an IRQ is pending
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* for a particular HART context, the PLIC will raise an interrupt on that HART context's
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* External interrupt pending(EIP) pin and trigger an interrupt. The HART can then claim
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* the IRQ message by communicating with the PLIC where it will receive the highest
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* priority pending interrupt. The PLIC will deassert the EIP pin when there are
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* no more pending interrupts for that HART. When the HART has finished processing
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* the IRQ it completes the claim by notifying the PLIC. Until an IRQ claim has
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* completed, the PLIC won't generate futher interrupts for that IRQ. In multicore
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* systems, if an IRQ is routed to multiple HARTs, the first HART to claim the IRQ
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* gets to process the IRQ and subsequent HARTs won't receive a claim for the same IRQ.
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*
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* We require each platform to provide the following functions:
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* interrupt_t plic_get_claim(void): If called when an IRQ is pending, returns
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* the pending priority and starts a claim process. Will return irqInvalid
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* if no IRQs are pending.
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* void plic_complete_claim(interrupt_t irq): Complete a claim process for an
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* interrupt.
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* void plic_mask_irq(bool_t disable, interrupt_t irq): Disables or enables an
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* IRQ at the PLIC.
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* void plic_irq_set_trigger(interrupt_t irq, bool_t edge_triggered): Configure
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* an IRQ source on the PLIC to be edge or level triggered. This function does
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* not need to be implemented if the PLIC doesn't support configuring this.
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* void plic_init_controller(void): Perform PLIC initialisation during boot.
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*/
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typedef uint32_t interrupt_t;
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typedef uint32_t irq_t;
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enum irqNumbers {
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irqInvalid = 6
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};
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#if defined(CONFIG_BUILD_SPIKE_QEMU)
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#include <plat/instance/qemu/hardware.h>
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#elif defined(CONFIG_BUILD_ROCKET_CHIP_ZEDBOARD)
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@ -41,12 +79,5 @@ enum IRQConstants {
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#define KERNEL_TIMER_IRQ INTERRUPT_TIMER
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#define IRQ_CNODE_SLOT_BITS 3
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enum irqNumbers {
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irqInvalid = 6
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};
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typedef uint32_t interrupt_t;
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typedef uint32_t irq_t;
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#endif /* !__ASSEMBLER__ */
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#endif
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