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aarch64,vspace: Remove pud cap type

Browse source 
Now the vspace_cap is used for all vspace roots and all other page
tables are referred to by page table caps.

Signed-off-by: Kent McLeod <kent@kry10.com>
This commit is contained in:
Kent McLeod 2022-03-01 00:07:28 +11:00 committed by Kent McLeod
parent dc808b3d76
commit cb8ee83f0c
11 changed files with 65 additions and 356 deletions
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21
include/arch/arm/arch/64/mode/object/structures.bf
View file

@ -32,7 +32,7 @@ block frame_cap {
padding 6
}
-- Forth-level page table
-- Page table caps
block page_table_cap {
field capPTMappedASID 16
field_high capPTBasePtr 48
@ -44,23 +44,7 @@ block page_table_cap {
padding 20
}
-- Second-level page table (page upper directory)
block page_upper_directory_cap {
field capPUDMappedASID 16
field_high capPUDBasePtr 48
field capType 5
field capPUDIsMapped 1
field_high capPUDMappedAddress 10
#if defined (CONFIG_ARM_SMMU) && defined (AARCH64_VSPACE_S2_START_L1)
field capPUDMappedCB 8
padding 40
#else
padding 48
#endif
}
-- First-level page table (page global directory)
-- First-level page table (vspace_root)
block vspace_cap {
field capMappedASID 16
field_high capPTBasePtr 48
@ -164,7 +148,6 @@ tagged_union cap capType {
-- 5-bit tag arch caps
tag frame_cap 1
tag page_table_cap 3
tag page_upper_directory_cap 7
tag vspace_cap 9
tag asid_control_cap 11
tag asid_pool_cap 13

19
include/arch/arm/arch/64/mode/object/structures.h
View file

@ -30,16 +30,6 @@ enum vm_rights {
};
typedef word_t vm_rights_t;
/* If hypervisor support for aarch64 is enabled and we run on processors with
* 40-bit PA, the stage-2 translation for EL1/EL0 uses a 3-level translation, skipping the PGD level.
* Yet the kernel will still use a stage-1 translation with 48 bit input addresses and a 4-level
* translation. Therefore, PUD and PGD size for the kernel can be different from EL1/EL0
* so we do not use the libsel4 definitions */
#define PUD_SIZE_BITS 12
#define PUD_INDEX_BITS 9
#define UPUD_SIZE_BITS seL4_PUDBits
#define UPUD_INDEX_BITS seL4_PUDIndexBits
#define PTE_SIZE_BITS seL4_PageTableEntryBits
#define PT_INDEX_BITS seL4_PageTableIndexBits
@ -104,9 +94,6 @@ static inline word_t CONST cap_get_archCapSizeBits(cap_t cap)
case cap_page_table_cap:
return seL4_PageTableBits;
case cap_page_upper_directory_cap:
return seL4_PUDBits;
case cap_vspace_cap:
return seL4_VSpaceBits;
@ -141,9 +128,6 @@ static inline bool_t CONST cap_get_archCapIsPhysical(cap_t cap)
case cap_page_table_cap:
return true;
case cap_page_upper_directory_cap:
return true;
case cap_vspace_cap:
return true;
@ -177,9 +161,6 @@ static inline void *CONST cap_get_archCapPtr(cap_t cap)
case cap_page_table_cap:
return PT_PTR(cap_page_table_cap_get_capPTBasePtr(cap));
case cap_page_upper_directory_cap:
return PT_PTR(cap_page_upper_directory_cap_get_capPUDBasePtr(cap));
case cap_vspace_cap:
return VSPACE_PTR(cap_vspace_cap_get_capPTBasePtr(cap));

83
libsel4/sel4_arch_include/aarch64/interfaces/sel4arch.xml
View file

@ -207,87 +207,4 @@
</error>
</method>
</interface>
<interface name="seL4_ARM_PageUpperDirectory" manual_name="Page Upper Directory"
cap_description="Capability to the upper page directory being operated on.">
<method id="ARMPageUpperDirectoryMap" name="Map">
<condition>
<not>
<and>
<config var="CONFIG_ARM_HYPERVISOR_SUPPORT"/>
<config var="CONFIG_ARM_PA_SIZE_BITS_40"/>
</and>
</not>
</condition>
<brief>
Map an upper page directory
</brief>
<description>
Map an upper page directory (level 1) to a top level translation table (level 0).
</description>
<param dir="in" name="vspace" type="seL4_CPtr"
description="Top level translation table. Must be assigned to an ASID pool."/>
<param dir="in" name="vaddr" type="seL4_Word"
description="Virtual address"/>
<param dir="in" name="attr" type="seL4_ARM_VMAttributes">
<description>
VM Attributes for the mapping.<docref>Possible values for this type are given in <autoref label="ch:vspace"/> .</docref>
</description>
</param>
<error name="seL4_DeleteFirst">
<description>
A mapping already exists for this level in <texttt text="vspace"/> at <texttt text="vaddr"/>.
</description>
</error>
<error name="seL4_FailedLookup">
<description>
The <texttt text="vspace"/> is not assigned to an ASID pool.
</description>
</error>
<error name="seL4_IllegalOperation">
<description>
The <texttt text="_service"/> is a CPtr to a capability of the wrong type.
</description>
</error>
<error name="seL4_InvalidArgument">
<description>
The <texttt text="vaddr"/> is in the kernel virtual address range.
</description>
</error>
<error name="seL4_InvalidCapability">
<description>
The <texttt text="_service"/> or <texttt text="vspace"/> is a CPtr to a capability of the wrong type.
Or, <texttt text="vspace"/> is not assigned to an ASID pool.
Or, <texttt text="_service"/> is already mapped in a VSpace.
</description>
</error>
</method>
<method id="ARMPageUpperDirectoryUnmap" name="Unmap">
<condition>
<not>
<and>
<config var="CONFIG_ARM_HYPERVISOR_SUPPORT"/>
<config var="CONFIG_ARM_PA_SIZE_BITS_40"/>
</and>
</not>
</condition>
<description>
TODO
</description>
<error name="seL4_IllegalOperation">
<description>
The <texttt text="_service"/> is a CPtr to a capability of the wrong type.
</description>
</error>
<error name="seL4_InvalidCapability">
<description>
The <texttt text="_service"/> is a CPtr to a capability of the wrong type.
</description>
</error>
<error name="seL4_RevokeFirst">
<description>
A copy of the <texttt text="_service"/> capability exists.
</description>
</error>
</method>
</interface>
</api>

26
libsel4/sel4_arch_include/aarch64/sel4/sel4_arch/constants.h
View file

@ -193,31 +193,18 @@ typedef enum {
#define seL4_IOPageTableBits 12
#define seL4_WordSizeBits 3
#define seL4_PUDEntryBits 3
#define seL4_VSpaceEntryBits 3
#if defined(CONFIG_ARM_HYPERVISOR_SUPPORT) && defined (CONFIG_ARM_PA_SIZE_BITS_40)
/* for a 3 level translation, we skip the PGD */
#define seL4_PGDBits 0
#define seL4_PGDEntryBits 0
#define seL4_PGDIndexBits 0
#define seL4_PUDBits 13
#define seL4_PUDIndexBits 10
#define seL4_VSpaceBits seL4_PUDBits
#define seL4_VSpaceIndexBits seL4_PUDIndexBits
#define seL4_ARM_VSpaceObject seL4_ARM_PageUpperDirectoryObject
#define seL4_VSpaceBits 13
#define seL4_VSpaceIndexBits 10
#else
#define seL4_PGDBits 12
#define seL4_PGDEntryBits 3
#define seL4_PGDIndexBits 9
#define seL4_PUDBits 12
#define seL4_PUDIndexBits 9
#define seL4_VSpaceBits seL4_PGDBits
#define seL4_VSpaceIndexBits seL4_PGDIndexBits
#define seL4_ARM_VSpaceObject seL4_ARM_PageGlobalDirectoryObject
#define seL4_VSpaceBits 12
#define seL4_VSpaceIndexBits 9
#endif
#define seL4_ARM_VCPUBits 12
@ -233,8 +220,7 @@ typedef enum {
#ifndef __ASSEMBLER__
SEL4_SIZE_SANITY(seL4_PageTableEntryBits, seL4_PageTableIndexBits, seL4_PageTableBits);
SEL4_SIZE_SANITY(seL4_WordSizeBits, seL4_ASIDPoolIndexBits, seL4_ASIDPoolBits);
SEL4_SIZE_SANITY(seL4_PGDEntryBits, seL4_PGDIndexBits, seL4_PGDBits);
SEL4_SIZE_SANITY(seL4_PUDEntryBits, seL4_PUDIndexBits, seL4_PUDBits);
SEL4_SIZE_SANITY(seL4_VSpaceEntryBits, seL4_VSpaceIndexBits, seL4_VSpaceBits);
#endif
#ifdef CONFIG_ENABLE_BENCHMARKS

27
libsel4/sel4_arch_include/aarch64/sel4/sel4_arch/deprecated.h
View file

@ -16,3 +16,30 @@
#define seL4_PageDirEntryBits seL4_PageTableEntryBits
#define seL4_PageDirIndexBits seL4_PageTableIndexBits
#define seL4_ARM_PageDirectoryObject seL4_ARM_PageTableObject
#define seL4_PUDEntryBits 3
#if defined(CONFIG_ARM_HYPERVISOR_SUPPORT) && defined (CONFIG_ARM_PA_SIZE_BITS_40)
#define seL4_PGDBits 0
#define seL4_PGDEntryBits 0
#define seL4_PGDIndexBits 0
#define seL4_PUDBits 13
#define seL4_PUDIndexBits 10
#define seL4_ARM_PageUpperDirectoryObject seL4_ARM_VSpaceObject
#else
#define seL4_PGDBits 12
#define seL4_PGDEntryBits 3
#define seL4_PGDIndexBits 9
#define seL4_PUDBits 12
#define seL4_PUDIndexBits 9
#define seL4_ARM_PageGlobalDirectoryObject seL4_ARM_VSpaceObject
#define seL4_ARM_PageUpperDirectoryObject seL4_ARM_PageTableObject
#define seL4_ARM_PageUpperDirectory seL4_ARM_PageTable;
#define seL4_ARM_PageUpperDirectory_Map seL4_ARM_PageTable_Map
#define seL4_ARM_PageUpperDirectory_Unmap seL4_ARM_PageTable_Unmap
#endif

3
libsel4/sel4_arch_include/aarch64/sel4/sel4_arch/objecttype.h
View file

@ -8,7 +8,6 @@
typedef enum _mode_object {
seL4_ARM_HugePageObject = seL4_NonArchObjectTypeCount,
seL4_ARM_PageUpperDirectoryObject,
seL4_ARM_PageGlobalDirectoryObject,
seL4_ARM_VSpaceObject,
seL4_ModeObjectTypeCount
} seL4_ModeObjectType;

2
libsel4/tools/syscall_stub_gen.py
View file

@ -285,8 +285,6 @@ def init_arch_types(wordsize, args):
Type("seL4_ARM_VMAttributes", wordsize, wordsize),
CapType("seL4_ARM_Page", wordsize),
CapType("seL4_ARM_PageTable", wordsize),
CapType("seL4_ARM_PageUpperDirectory", wordsize),
CapType("seL4_ARM_PageGlobalDirectory", wordsize),
CapType("seL4_ARM_VSpace", wordsize),
CapType("seL4_ARM_ASIDControl", wordsize),
CapType("seL4_ARM_ASIDPool", wordsize),

141
src/arch/arm/64/kernel/vspace.c
View file

@ -216,7 +216,7 @@ BOOT_CODE void map_kernel_window(void)
#endif
assert(IS_ALIGNED(PPTR_BASE, seL4_LargePageBits));
/* verify that the kernel device window is 1gb aligned and 1gb in size */
assert(GET_KPT_INDEX(PPTR_TOP, KLVL_FRM_ARM_PT_LVL(1)) == BIT(PUD_INDEX_BITS) - 1);
assert(GET_KPT_INDEX(PPTR_TOP, KLVL_FRM_ARM_PT_LVL(1)) == BIT(PT_INDEX_BITS) - 1);
assert(IS_ALIGNED(PPTR_TOP, seL4_HugePageBits));
/* place the PUD into the PGD */
@ -253,7 +253,7 @@ BOOT_CODE void map_kernel_window(void)
/* put the PD into the PUD for device window */
armKSGlobalKernelPUD[GET_KPT_INDEX(PPTR_TOP, KLVL_FRM_ARM_PT_LVL(1))] = pte_pte_table_new(
addrFromKPPtr(&armKSGlobalKernelPDs[BIT(PUD_INDEX_BITS) - 1][0])
addrFromKPPtr(&armKSGlobalKernelPDs[BIT(PT_INDEX_BITS) - 1][0])
);
/* put the PT into the PD for device window */
@ -408,10 +408,10 @@ static BOOT_CODE cap_t create_it_pd_cap(cap_t vspace_cap, pptr_t pptr, vptr_t vp
static BOOT_CODE void map_it_pud_cap(cap_t vspace_cap, cap_t pud_cap)
{
pte_t *pgd = PT_PTR(pptr_of_cap(vspace_cap));
pte_t *pud = PT_PTR(cap_page_upper_directory_cap_get_capPUDBasePtr(pud_cap));
vptr_t vptr = cap_page_upper_directory_cap_get_capPUDMappedAddress(pud_cap);
pte_t *pud = PT_PTR(cap_page_table_cap_get_capPTBasePtr(pud_cap));
vptr_t vptr = cap_page_table_cap_get_capPTMappedAddress(pud_cap);
assert(cap_page_upper_directory_cap_get_capPUDIsMapped(pud_cap));
assert(cap_page_table_cap_get_capPTIsMapped(pud_cap));
*(pgd + GET_UPT_INDEX(vptr, ULVL_FRM_ARM_PT_LVL(0))) = pte_pte_table_new(
pptr_to_paddr(pud));
@ -420,11 +420,11 @@ static BOOT_CODE void map_it_pud_cap(cap_t vspace_cap, cap_t pud_cap)
static BOOT_CODE cap_t create_it_pud_cap(cap_t vspace_cap, pptr_t pptr, vptr_t vptr, asid_t asid)
{
cap_t cap;
cap = cap_page_upper_directory_cap_new(
asid, /* capPUDMappedASID */
pptr, /* capPUDBasePtr */
1, /* capPUDIsMapped */
vptr /* capPUDMappedAddress */
cap = cap_page_table_cap_new(
asid, /* capPTMappedASID */
pptr, /* capPTBasePtr */
1, /* capPTIsMapped */
vptr /* capPTMappedAddress */
);
map_it_pud_cap(vspace_cap, cap);
return cap;
@ -1147,29 +1147,6 @@ static exception_t performVSpaceFlush(int invLabel, vspace_root_t *vspaceRoot, a
return EXCEPTION_NONE;
}
#ifndef AARCH64_VSPACE_S2_START_L1
static exception_t performUpperPageDirectoryInvocationMap(cap_t cap, cte_t *ctSlot, pte_t pgde, pte_t *pgdSlot)
{
ctSlot->cap = cap;
*pgdSlot = pgde;
cleanByVA_PoU((vptr_t)pgdSlot, pptr_to_paddr(pgdSlot));
return EXCEPTION_NONE;
}
static exception_t performUpperPageDirectoryInvocationUnmap(cap_t cap, cte_t *ctSlot)
{
if (cap_page_upper_directory_cap_get_capPUDIsMapped(cap)) {
pte_t *pud = PT_PTR(cap_page_upper_directory_cap_get_capPUDBasePtr(cap));
unmapPageTable(cap_page_upper_directory_cap_get_capPUDMappedASID(cap),
cap_page_upper_directory_cap_get_capPUDMappedAddress(cap), pud);
clearMemory_PT((void *)pud, cap_get_capSizeBits(cap));
}
cap_page_upper_directory_cap_ptr_set_capPUDIsMapped(&(ctSlot->cap), 0);
return EXCEPTION_NONE;
}
#endif
static exception_t performPageTableInvocationMap(cap_t cap, cte_t *ctSlot, pte_t pte, pte_t *ptSlot)
{
@ -1393,100 +1370,6 @@ static exception_t decodeARMVSpaceRootInvocation(word_t invLabel, unsigned int l
}
}
#ifndef AARCH64_VSPACE_S2_START_L1
static exception_t decodeARMPageUpperDirectoryInvocation(word_t invLabel, unsigned int length,
cte_t *cte, cap_t cap, word_t *buffer)
{
cap_t pgdCap;
vspace_root_t *pgd;
pte_t pgde;
asid_t asid;
vptr_t vaddr;
lookupPTSlot_ret_t pgdSlot;
findVSpaceForASID_ret_t find_ret;
if (invLabel == ARMPageUpperDirectoryUnmap) {
if (unlikely(!isFinalCapability(cte))) {
current_syscall_error.type = seL4_RevokeFirst;
return EXCEPTION_SYSCALL_ERROR;
}
setThreadState(NODE_STATE(ksCurThread), ThreadState_Restart);
return performUpperPageDirectoryInvocationUnmap(cap, cte);
}
if (unlikely(invLabel != ARMPageUpperDirectoryMap)) {
current_syscall_error.type = seL4_IllegalOperation;
return EXCEPTION_SYSCALL_ERROR;
}
if (unlikely(length < 2 || current_extra_caps.excaprefs[0] == NULL)) {
current_syscall_error.type = seL4_TruncatedMessage;
return EXCEPTION_SYSCALL_ERROR;
}
if (unlikely(cap_page_upper_directory_cap_get_capPUDIsMapped(cap))) {
current_syscall_error.type = seL4_InvalidCapability;
current_syscall_error.invalidCapNumber = 0;
return EXCEPTION_SYSCALL_ERROR;
}
vaddr = getSyscallArg(0, buffer) & (~MASK(GET_ULVL_PGSIZE_BITS(ULVL_FRM_ARM_PT_LVL(0))));
pgdCap = current_extra_caps.excaprefs[0]->cap;
if (unlikely(!isValidNativeRoot(pgdCap))) {
current_syscall_error.type = seL4_InvalidCapability;
current_syscall_error.invalidCapNumber = 1;
return EXCEPTION_SYSCALL_ERROR;
}
pgd = VSPACE_PTR(cap_vspace_cap_get_capPTBasePtr(pgdCap));
asid = cap_vspace_cap_get_capMappedASID(pgdCap);
if (unlikely(vaddr > USER_TOP)) {
current_syscall_error.type = seL4_InvalidArgument;
current_syscall_error.invalidArgumentNumber = 0;
return EXCEPTION_SYSCALL_ERROR;
}
find_ret = findVSpaceForASID(asid);
if (unlikely(find_ret.status != EXCEPTION_NONE)) {
current_syscall_error.type = seL4_FailedLookup;
current_syscall_error.failedLookupWasSource = false;
return EXCEPTION_SYSCALL_ERROR;
}
if (unlikely(find_ret.vspace_root != pgd)) {
current_syscall_error.type = seL4_InvalidCapability;
current_syscall_error.invalidCapNumber = 1;
return EXCEPTION_SYSCALL_ERROR;
}
pgdSlot = lookupPTSlot(pgd, vaddr);
if (unlikely(pgdSlot.ptBitsLeft > GET_ULVL_PGSIZE_BITS(ULVL_FRM_ARM_PT_LVL(0)))) {
current_syscall_error.type = seL4_FailedLookup;
current_syscall_error.failedLookupWasSource = false;
return EXCEPTION_SYSCALL_ERROR;
}
if (unlikely(pte_pte_table_ptr_get_present(pgdSlot.ptSlot) ||
pgdSlot.ptBitsLeft < GET_ULVL_PGSIZE_BITS(ULVL_FRM_ARM_PT_LVL(0)))) {
current_syscall_error.type = seL4_DeleteFirst;
return EXCEPTION_SYSCALL_ERROR;
}
pgde = pte_pte_table_new(
pptr_to_paddr(PTE_PTR(cap_page_upper_directory_cap_get_capPUDBasePtr(cap))));
cap_page_upper_directory_cap_ptr_set_capPUDIsMapped(&cap, 1);
cap_page_upper_directory_cap_ptr_set_capPUDMappedASID(&cap, asid);
cap_page_upper_directory_cap_ptr_set_capPUDMappedAddress(&cap, vaddr);
setThreadState(NODE_STATE(ksCurThread), ThreadState_Restart);
return performUpperPageDirectoryInvocationMap(cap, cte, pgde, pgdSlot.ptSlot);
}
#endif
static exception_t decodeARMPageTableInvocation(word_t invLabel, unsigned int length,
cte_t *cte, cap_t cap, word_t *buffer)
@ -1758,10 +1641,6 @@ exception_t decodeARMMMUInvocation(word_t invLabel, word_t length, cptr_t cptr,
switch (cap_get_capType(cap)) {
case cap_vspace_cap:
return decodeARMVSpaceRootInvocation(invLabel, length, cte, cap, buffer);
#ifndef AARCH64_VSPACE_S2_START_L1
case cap_page_upper_directory_cap:
return decodeARMPageUpperDirectoryInvocation(invLabel, length, cte, cap, buffer);
#endif
case cap_page_table_cap:
return decodeARMPageTableInvocation(invLabel, length, cte, cap, buffer);

36
src/arch/arm/64/machine/capdl.c
View file

@ -195,13 +195,15 @@ static void arm64_cap_pud_print_slots(void *pgdSlot_or_vspace, vptr_t vptr)
{
#ifdef AARCH64_VSPACE_S2_START_L1
pte_t *pud = pgdSlot_or_vspace;
word_t index_bits = seL4_VSpaceIndexBits;
printf("%p_pd {\n", pgdSlot_or_vspace);
#else
pte_t *pud = paddr_to_pptr(pte_pte_table_ptr_get_pt_base_address(pgdSlot_or_vspace));
word_t index_bits = seL4_PageTableIndexBits;
printf("pud_%p_%04lu {\n", pgdSlot_or_vspace, GET_UPT_INDEX(vptr, ULVL_FRM_ARM_PT_LVL(0)));
#endif
for (word_t i = 0; i < BIT(UPUD_INDEX_BITS); i++) {
for (word_t i = 0; i < BIT(index_bits); i++) {
pte_t *pudSlot = pud + i;
if (pte_ptr_get_pte_type(pudSlot) == pte_pte_table) {
printf("0x%lx: pd_%p_%04lu\n", i, pudSlot, i);
@ -210,7 +212,7 @@ static void arm64_cap_pud_print_slots(void *pgdSlot_or_vspace, vptr_t vptr)
printf("}\n"); /* pgd/pud */
for (word_t i = 0; i < BIT(UPUD_INDEX_BITS); i++) {
for (word_t i = 0; i < BIT(index_bits); i++) {
pte_t *pudSlot = pud + GET_UPT_INDEX(i, ULVL_FRM_ARM_PT_LVL(1));
if (pte_ptr_get_pte_type(pudSlot) == pte_pte_table) {
arm64_cap_pd_print_slots(pudSlot, vptr + (i * GET_ULVL_PGSIZE(ULVL_FRM_ARM_PT_LVL(1))));
@ -261,22 +263,11 @@ void print_cap_arch(cap_t cap)
{
switch (cap_get_capType(cap)) {
case cap_page_table_cap:
case cap_page_upper_directory_cap: {
asid_t asid = 0;
vptr_t vptr = 0;
pte_t *target_pt = NULL;
switch (cap_get_capType(cap)) {
case cap_page_table_cap:
asid = cap_page_table_cap_get_capPTMappedASID(cap);
vptr = cap_page_table_cap_get_capPTMappedAddress(cap);
target_pt = PT_PTR(cap_page_table_cap_get_capPTBasePtr(cap));
break;
case cap_page_upper_directory_cap:
asid = cap_page_upper_directory_cap_get_capPUDMappedASID(cap);
vptr = cap_page_upper_directory_cap_get_capPUDMappedAddress(cap);
target_pt = PT_PTR(cap_page_upper_directory_cap_get_capPUDBasePtr(cap));
}
case cap_page_table_cap: {
asid_t asid = cap_page_table_cap_get_capPTMappedASID(cap);
vptr_t vptr = cap_page_table_cap_get_capPTMappedAddress(cap);
pte_t *target_pt = PT_PTR(cap_page_table_cap_get_capPTBasePtr(cap));
findVSpaceForASID_ret_t find_ret = findVSpaceForASID(asid);
pte_t *ptSlot = NULL;
pte_t *pt = (pte_t *)find_ret.vspace_root;
@ -356,7 +347,6 @@ void print_object_arch(cap_t cap)
switch (cap_get_capType(cap)) {
case cap_frame_cap:
case cap_page_table_cap:
case cap_page_upper_directory_cap:
case cap_vspace_cap:
/* don't need to deal with these objects since they get handled from vtable */
break;
@ -444,8 +434,12 @@ void arm64_obj_pd_print_slots(pte_t *pudSlot)
void arm64_obj_pud_print_slots(void *pgdSlot_or_vspace)
{
pte_t *pud = paddr_to_pptr(pte_pte_table_ptr_get_pt_base_address(pgdSlot_or_vspace));
for (word_t i = 0; i < BIT(UPUD_INDEX_BITS); i++) {
#ifdef AARCH64_VSPACE_S2_START_L1
word_t index_bits = seL4_VSpaceIndexBits;
#else
word_t index_bits = seL4_PageTableIndexBits;
#endif
for (word_t i = 0; i < BIT(index_bits); i++) {
pte_t *pudSlot = pud + i;
switch (pte_ptr_get_pte_type(pudSlot)) {

2
src/arch/arm/64/model/statedata.c
View file

@ -85,7 +85,7 @@ asid_pool_t *armKSASIDTable[BIT(asidHighBits)];
vspace_root_t armKSGlobalUserVSpace[BIT(seL4_VSpaceIndexBits)] ALIGN_BSS(BIT(seL4_VSpaceBits));
pte_t armKSGlobalKernelPGD[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
pte_t armKSGlobalKernelPUD[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PUDBits));
pte_t armKSGlobalKernelPUD[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
pte_t armKSGlobalKernelPDs[BIT(PT_INDEX_BITS)][BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
pte_t armKSGlobalKernelPT[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));

61
src/arch/arm/64/object/objecttype.c
View file

@ -44,18 +44,6 @@ deriveCap_ret_t Arch_deriveCap(cte_t *slot, cap_t cap)
}
return ret;
case cap_page_upper_directory_cap:
if (cap_page_upper_directory_cap_get_capPUDIsMapped(cap)) {
ret.cap = cap;
ret.status = EXCEPTION_NONE;
} else {
userError("Deriving a PUD cap without an assigned ASID");
current_syscall_error.type = seL4_IllegalOperation;
ret.cap = cap_null_cap_new();
ret.status = EXCEPTION_SYSCALL_ERROR;
}
return ret;
case cap_page_table_cap:
if (cap_page_table_cap_get_capPTIsMapped(cap)) {
ret.cap = cap;
@ -148,28 +136,6 @@ finaliseCap_ret_t Arch_finaliseCap(cap_t cap, bool_t final)
}
break;
case cap_page_upper_directory_cap:
#ifdef AARCH64_VSPACE_S2_START_L1
#ifdef CONFIG_ARM_SMMU
if (cap_page_upper_directory_cap_get_capPGDMappedCB(cap) != CB_INVALID) {
smmu_cb_delete_vspace(cap_page_upper_directory_cap_get_capPUDMappedCB(cap),
cap_page_upper_directory_cap_get_capPUDMappedASID(cap));
}
#endif
if (final && cap_page_upper_directory_cap_get_capPUDIsMapped(cap)) {
deleteASID(cap_page_upper_directory_cap_get_capPUDMappedASID(cap),
PTE_PTR(cap_page_upper_directory_cap_get_capPUDBasePtr(cap)));
}
#else
if (final && cap_page_upper_directory_cap_get_capPUDIsMapped(cap)) {
unmapPageTable(cap_page_upper_directory_cap_get_capPUDMappedASID(cap),
cap_page_upper_directory_cap_get_capPUDMappedAddress(cap),
PTE_PTR(cap_page_upper_directory_cap_get_capPUDBasePtr(cap)));
}
#endif
break;
case cap_page_table_cap:
if (final && cap_page_table_cap_get_capPTIsMapped(cap)) {
unmapPageTable(cap_page_table_cap_get_capPTMappedASID(cap),
@ -237,13 +203,6 @@ bool_t CONST Arch_sameRegionAs(cap_t cap_a, cap_t cap_b)
}
break;
case cap_page_upper_directory_cap:
if (cap_get_capType(cap_b) == cap_page_upper_directory_cap) {
return cap_page_upper_directory_cap_get_capPUDBasePtr(cap_a) ==
cap_page_upper_directory_cap_get_capPUDBasePtr(cap_b);
}
break;
case cap_vspace_cap:
if (cap_get_capType(cap_b) == cap_vspace_cap) {
return cap_vspace_cap_get_capPTBasePtr(cap_a) ==
@ -338,12 +297,8 @@ word_t Arch_getObjectSize(word_t t)
return ARMHugePageBits;
case seL4_ARM_PageTableObject:
return seL4_PageTableBits;
case seL4_ARM_PageUpperDirectoryObject:
return seL4_PUDBits;
#ifndef AARCH64_VSPACE_S2_START_L1
case seL4_ARM_PageGlobalDirectoryObject:
return seL4_PGDBits;
#endif
case seL4_ARM_VSpaceObject:
return seL4_VSpaceBits;
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
case seL4_ARM_VCPUObject:
return VCPU_SIZE_BITS;
@ -386,8 +341,7 @@ cap_t Arch_createObject(object_t t, void *regionBase, word_t userSize, bool_t de
VMReadWrite, /* capFVMRights */
!!deviceMemory /* capFIsDevice */
);
#ifndef AARCH64_VSPACE_S2_START_L1
case seL4_ARM_PageGlobalDirectoryObject:
case seL4_ARM_VSpaceObject:
#ifdef CONFIG_ARM_SMMU
return cap_vspace_cap_new(
@ -404,15 +358,6 @@ cap_t Arch_createObject(object_t t, void *regionBase, word_t userSize, bool_t de
0 /* capIsMapped */
);
#endif /*!CONFIG_ARM_SMMU*/
#endif /*!AARCH64_VSPACE_S2_START_L1*/
case seL4_ARM_PageUpperDirectoryObject:
return cap_page_upper_directory_cap_new(
asidInvalid, /* capPUDMappedASID */
(word_t)regionBase, /* capPUDBasePtr */
0, /* capPUDIsMapped */
0 /* capPUDMappedAddress */
);
case seL4_ARM_PageTableObject:
return cap_page_table_cap_new(
asidInvalid, /* capPTMappedASID */