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trivial: style

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This commit is contained in:
Adrian Danis 2015-04-17 13:52:37 +10:00
parent 8abdf6c5ed
commit e581882c3c
3 changed files with 8 additions and 7 deletions
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2
include/arch/ia32/arch/machine.h
View file

@ -39,7 +39,7 @@
#define MODEL_ID(x) ( ((x & 0xf0000) >> 16) + (x & 0xf0) )
/* This article discloses prefetcher control on Intel processors; Nehalem, Westmere, Sandy Bridge,
/* This article discloses prefetcher control on Intel processors; Nehalem, Westmere, Sandy Bridge,
Ivy Bridge, Haswell, and Broadwell. It is currently undocumented in the regular intel manuals.
https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processors */
#define IA32_PREFETCHER_MSR 0x1A4

2
src/arch/ia32/kernel/boot.c
View file

@ -575,7 +575,7 @@ init_node_cpu(
if (!apic_init(apic_khz, mask_legacy_irqs)) {
return false;
}
#ifdef CONFIG_DEBUG_DISABLE_PREFETCHERS
if (!disablePrefetchers()) {
return false;

11
src/arch/ia32/machine/hardware.c
View file

@ -84,16 +84,17 @@ void flushCacheRange(void* vaddr, uint32_t size_bits)
}
/* Disables as many prefetchers as possible */
BOOT_CODE bool_t
BOOT_CODE bool_t
disablePrefetchers()
{
uint32_t version_info;
uint32_t low, high;
uint32_t low, high;
int i;
uint32_t valid_models[] = { BROADWELL_MODEL_ID, HASWELL_MODEL_ID, IVY_BRIDGE_MODEL_ID,
SANDY_BRIDGE_1_MODEL_ID, SANDY_BRIDGE_2_MODEL_ID, WESTMERE_1_MODEL_ID, WESTMERE_2_MODEL_ID,
WESTMERE_3_MODEL_ID, NEHALEM_1_MODEL_ID, NEHALEM_2_MODEL_ID, NEHALEM_3_MODEL_ID };
uint32_t valid_models[] = { BROADWELL_MODEL_ID, HASWELL_MODEL_ID, IVY_BRIDGE_MODEL_ID,
SANDY_BRIDGE_1_MODEL_ID, SANDY_BRIDGE_2_MODEL_ID, WESTMERE_1_MODEL_ID, WESTMERE_2_MODEL_ID,
WESTMERE_3_MODEL_ID, NEHALEM_1_MODEL_ID, NEHALEM_2_MODEL_ID, NEHALEM_3_MODEL_ID
};
version_info = ia32_cpuid_eax(0x1, 0x0);