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x86: Rename constants and functions to have X86 prefix instead of IA32 prefix

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This commit is contained in:
Adrian Danis 2015-11-06 15:19:50 +11:00
parent 6729ce7823
commit ef85f94a99
9 changed files with 56 additions and 57 deletions
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19
include/arch/x86/arch/32/mode/machine.h
View file

@ -88,7 +88,7 @@ static inline void clearMemory(void* ptr, word_t bits)
/* Initialises MSRs required to setup sysenter and sysexit */
void init_sysenter_msrs(void);
static uint64_t ia32_rdmsr(const uint32_t reg)
static uint64_t x86_rdmsr(const uint32_t reg)
{
uint64_t value;
asm volatile("rdmsr" : "=A"(value) : "c"(reg));
@ -96,25 +96,24 @@ static uint64_t ia32_rdmsr(const uint32_t reg)
}
/* Read model specific register */
static inline uint32_t ia32_rdmsr_low(const uint32_t reg)
static inline uint32_t x86_rdmsr_low(const uint32_t reg)
{
return (uint32_t)ia32_rdmsr(reg);
return (uint32_t)x86_rdmsr(reg);
}
static inline uint32_t ia32_rdmsr_high(const uint32_t reg)
static inline uint32_t x86_rdmsr_high(const uint32_t reg)
{
return (uint32_t)(ia32_rdmsr(reg) >> 32ull);
return (uint32_t)(x86_rdmsr(reg) >> 32ull);
}
/* Write model specific register */
static inline void ia32_wrmsr(const uint32_t reg, const uint32_t val_high, const uint32_t val_low)
static inline void x86_wrmsr(const uint32_t reg, const uint64_t val)
{
uint64_t val = ((uint64_t)val_high << 32ull) | (uint64_t)val_low;
asm volatile("wrmsr" :: "A"(val), "c"(reg));
}
/* Read different parts of CPUID */
static inline uint32_t ia32_cpuid_edx(uint32_t eax, uint32_t ecx)
static inline uint32_t x86_cpuid_edx(uint32_t eax, uint32_t ecx)
{
uint32_t edx, ebx;
asm volatile("cpuid"
@ -127,7 +126,7 @@ static inline uint32_t ia32_cpuid_edx(uint32_t eax, uint32_t ecx)
return edx;
}
static inline uint32_t ia32_cpuid_eax(uint32_t eax, uint32_t ecx)
static inline uint32_t x86_cpuid_eax(uint32_t eax, uint32_t ecx)
{
uint32_t edx, ebx;
asm volatile("cpuid"
@ -141,7 +140,7 @@ static inline uint32_t ia32_cpuid_eax(uint32_t eax, uint32_t ecx)
}
/* Read/write memory fence */
static inline void ia32_mfence(void)
static inline void x86_mfence(void)
{
asm volatile("mfence" ::: "memory");
}

14
include/arch/x86/arch/machine/hardware.h
View file

@ -29,18 +29,18 @@ enum vm_page_size {
typedef word_t vm_page_size_t;
enum frameSizeConstants {
IA32_4K_bits = 12,
IA32_2M_bits = 21,
IA32_4M_bits = 22,
IA32_1G_bits = 30
X86_4K_bits = 12,
X86_2M_bits = 21,
X86_4M_bits = 22,
X86_1G_bits = 30
};
#define PAGE_BITS IA32_4K_bits
#define PAGE_BITS X86_4K_bits
#ifdef CONFIG_PAE_PAGING
#define LARGE_PAGE_BITS IA32_2M_bits
#define LARGE_PAGE_BITS X86_2M_bits
#else
#define LARGE_PAGE_BITS IA32_4M_bits
#define LARGE_PAGE_BITS X86_4M_bits
#endif
/* Any changes to this function need to be replicated in pageBitsForSize_phys.

4
include/plat/pc99/plat/32/plat_mode/machine/hardware.h
View file

@ -16,9 +16,9 @@
#define PADDR_LOAD 0x00100000
#define PPTR_BASE 0xe0000000
#ifdef CONFIG_PAE_PAGING
#define PPTR_USER_TOP (PPTR_BASE & (~MASK(IA32_1G_bits)))
#define PPTR_USER_TOP (PPTR_BASE & (~MASK(X86_1G_bits)))
#else
#define PPTR_USER_TOP (PPTR_BASE & (~MASK(IA32_4M_bits)))
#define PPTR_USER_TOP (PPTR_BASE & (~MASK(X86_4M_bits)))
#endif
#if CONFIG_MAX_NUM_TRACE_POINTS > 0
#define PPTR_TOP (-BIT(LARGE_PAGE_BITS + 1))

18
src/arch/x86/32/kernel/vspace_32paging.c
View file

@ -70,10 +70,10 @@ init_boot_pd(void)
word_t i;
/* identity mapping from 0 up to PPTR_BASE (virtual address) */
for (i = 0; i < (PPTR_BASE >> IA32_4M_bits); i++) {
for (i = 0; i < (PPTR_BASE >> X86_4M_bits); i++) {
pde_pde_large_ptr_new_phys(
_boot_pd + i,
i << IA32_4M_bits, /* physical address */
i << X86_4M_bits, /* physical address */
0, /* pat */
0, /* avl */
1, /* global */
@ -88,10 +88,10 @@ init_boot_pd(void)
}
/* mapping of PPTR_BASE (virtual address) to PADDR_BASE up to end of virtual address space */
for (i = 0; i < ((-PPTR_BASE) >> IA32_4M_bits); i++) {
for (i = 0; i < ((-PPTR_BASE) >> X86_4M_bits); i++) {
pde_pde_large_ptr_new_phys(
_boot_pd + i + (PPTR_BASE >> IA32_4M_bits),
(i << IA32_4M_bits) + PADDR_BASE, /* physical address */
_boot_pd + i + (PPTR_BASE >> X86_4M_bits),
(i << X86_4M_bits) + PADDR_BASE, /* physical address */
0, /* pat */
0, /* avl */
1, /* global */
@ -115,7 +115,7 @@ map_it_pt_cap(cap_t vspace_cap, cap_t pt_cap)
assert(cap_page_table_cap_get_capPTIsMapped(pt_cap));
pde_pde_small_ptr_new(
pd + (vptr >> IA32_4M_bits),
pd + (vptr >> X86_4M_bits),
pptr_to_paddr(pt), /* pt_base_address */
0, /* avl */
0, /* accessed */
@ -144,10 +144,10 @@ map_it_frame_cap(cap_t pd_cap, cap_t frame_cap)
vptr_t vptr = cap_frame_cap_get_capFMappedAddress(frame_cap);
assert(cap_frame_cap_get_capFMappedASID(frame_cap) != 0);
pd += (vptr >> IA32_4M_bits);
pd += (vptr >> X86_4M_bits);
pt = paddr_to_pptr(pde_pde_small_ptr_get_pt_base_address(pd));
pte_ptr_new(
pt + ((vptr & MASK(IA32_4M_bits)) >> IA32_4K_bits),
pt + ((vptr & MASK(X86_4M_bits)) >> X86_4K_bits),
pptr_to_paddr(frame), /* page_base_address */
0, /* avl */
0, /* global */
@ -206,7 +206,7 @@ void copyGlobalMappings(void* new_vspace)
word_t i;
pde_t *newPD = (pde_t*)new_vspace;
for (i = PPTR_BASE >> IA32_4M_bits; i < BIT(PD_BITS); i++) {
for (i = PPTR_BASE >> X86_4M_bits; i < BIT(PD_BITS); i++) {
newPD[i] = ia32KSkernelPD[i];
}
}

28
src/arch/x86/32/kernel/vspace_pae.c
View file

@ -93,10 +93,10 @@ init_boot_pd(void)
}
/* identity mapping from 0 up to PPTR_BASE (virtual address) */
for (i = 0; (i << IA32_2M_bits) < PPTR_BASE; i++) {
for (i = 0; (i << X86_2M_bits) < PPTR_BASE; i++) {
pde_pde_large_ptr_new_phys(
_boot_pds + i,
i << IA32_2M_bits, /* physical address */
i << X86_2M_bits, /* physical address */
0, /* pat */
0, /* avl */
1, /* global */
@ -111,10 +111,10 @@ init_boot_pd(void)
}
/* mapping of PPTR_BASE (virtual address) to PADDR_BASE up to end of virtual address space */
for (i = 0; (i << IA32_2M_bits) < -PPTR_BASE; i++) {
for (i = 0; (i << X86_2M_bits) < -PPTR_BASE; i++) {
pde_pde_large_ptr_new_phys(
_boot_pds + i + (PPTR_BASE >> IA32_2M_bits),
(i << IA32_2M_bits) + PADDR_BASE, /* physical address */
_boot_pds + i + (PPTR_BASE >> X86_2M_bits),
(i << X86_2M_bits) + PADDR_BASE, /* physical address */
0, /* pat */
0, /* avl */
1, /* global */
@ -139,14 +139,14 @@ map_it_frame_cap(cap_t vspace_cap, cap_t frame_cap)
vptr_t vptr = cap_frame_cap_get_capFMappedAddress(frame_cap);
assert(cap_frame_cap_get_capFMappedASID(frame_cap) != 0);
pdpt += (vptr >> IA32_1G_bits);
pdpt += (vptr >> X86_1G_bits);
assert(pdpte_ptr_get_present(pdpt));
pd = paddr_to_pptr(pdpte_ptr_get_pd_base_address(pdpt));
pd += ( (vptr & MASK(IA32_1G_bits)) >> IA32_2M_bits);
pd += ( (vptr & MASK(X86_1G_bits)) >> X86_2M_bits);
assert(pde_pde_small_ptr_get_present(pd));
pt = paddr_to_pptr(pde_pde_small_ptr_get_pt_base_address(pd));
pte_ptr_new(
pt + ((vptr & MASK(IA32_2M_bits)) >> IA32_4K_bits),
pt + ((vptr & MASK(X86_2M_bits)) >> X86_4K_bits),
pptr_to_paddr(frame),
0, /* avl */
0, /* global */
@ -171,11 +171,11 @@ map_it_pt_cap(cap_t vspace_cap, cap_t pt_cap)
vptr_t vptr = cap_page_table_cap_get_capPTMappedAddress(pt_cap);
assert(cap_page_table_cap_get_capPTIsMapped(pt_cap));
pdpt += (vptr >> IA32_1G_bits);
pdpt += (vptr >> X86_1G_bits);
assert(pdpte_ptr_get_present(pdpt));
pd = paddr_to_pptr(pdpte_ptr_get_pd_base_address(pdpt));
pde_pde_small_ptr_new(
pd + (vptr >> IA32_2M_bits),
pd + (vptr >> X86_2M_bits),
pptr_to_paddr(pt),
0, /* avl*/
0, /* accessed */
@ -197,7 +197,7 @@ map_it_pd_cap(cap_t vspace_cap, cap_t pd_cap)
assert(cap_page_directory_cap_get_capPDIsMapped(pd_cap));
pdpte_ptr_new(
pdpt + (vptr >> IA32_1G_bits),
pdpt + (vptr >> X86_1G_bits),
pptr_to_paddr(pd),
0, /* avl */
0, /* cache_disabled */
@ -214,7 +214,7 @@ void copyGlobalMappings(void* new_vspace)
word_t i;
pdpte_t *pdpt = (pdpte_t*)new_vspace;
for (i = PPTR_BASE >> IA32_1G_bits; i < BIT(PDPT_BITS); i++) {
for (i = PPTR_BASE >> X86_1G_bits; i < BIT(PDPT_BITS); i++) {
pdpt[i] = ia32KSkernelPDPT[i];
}
}
@ -249,7 +249,7 @@ void *getValidNativeRoot(cap_t vspace_cap)
static inline pdpte_t *lookupPDPTSlot(void *vspace, vptr_t vptr)
{
pdpte_t *pdpt = PDPT_PTR(vspace);
return pdpt + (vptr >> IA32_1G_bits);
return pdpt + (vptr >> X86_1G_bits);
}
lookupPDSlot_ret_t lookupPDSlot(void *vspace, vptr_t vptr)
@ -379,7 +379,7 @@ decodeIA32PageDirectoryInvocation(
return EXCEPTION_SYSCALL_ERROR;
}
vaddr = getSyscallArg(0, buffer) & (~MASK(IA32_1G_bits));
vaddr = getSyscallArg(0, buffer) & (~MASK(X86_1G_bits));
attr = vmAttributesFromWord(getSyscallArg(1, buffer));
vspaceCap = extraCaps.excaprefs[0]->cap;

2
src/arch/x86/kernel/apic.c
View file

@ -78,7 +78,7 @@ apic_get_base_paddr(void)
{
apic_base_msr_t apic_base_msr;
apic_base_msr.words[0] = ia32_rdmsr_low(IA32_APIC_BASE_MSR);
apic_base_msr.words[0] = x86_rdmsr_low(IA32_APIC_BASE_MSR);
if (!apic_base_msr_get_enabled(apic_base_msr)) {
printf("APIC: Enabled bit not set\n");
}

2
src/arch/x86/kernel/boot_sys.c
View file

@ -410,7 +410,7 @@ BOOT_CODE static void
start_cpu(cpu_id_t cpu_id, paddr_t boot_fun_paddr)
{
/* memory fence needed before starting the other CPU */
ia32_mfence();
x86_mfence();
/* starting the other CPU */
apic_send_init_ipi(cpu_id);

8
src/arch/x86/kernel/vspace.c
View file

@ -853,12 +853,12 @@ init_pat_msr(void)
ia32_pat_msr_t pat_msr;
/* First verify PAT is supported by the machine.
* See section 11.12.1 of Volume 3 of the Intel manual */
if ( (ia32_cpuid_edx(0x1, 0x0) & BIT(16)) == 0) {
if ( (x86_cpuid_edx(0x1, 0x0) & BIT(16)) == 0) {
printf("PAT support not found\n");
return false;
}
pat_msr.words[0] = ia32_rdmsr_low(IA32_PAT_MSR);
pat_msr.words[1] = ia32_rdmsr_high(IA32_PAT_MSR);
pat_msr.words[0] = x86_rdmsr_low(IA32_PAT_MSR);
pat_msr.words[1] = x86_rdmsr_high(IA32_PAT_MSR);
/* Set up the PAT MSR to the Intel defaults, just in case
* they have been changed but a bootloader somewhere along the way */
ia32_pat_msr_ptr_set_pa0(&pat_msr, IA32_PAT_MT_WRITE_BACK);
@ -867,7 +867,7 @@ init_pat_msr(void)
ia32_pat_msr_ptr_set_pa3(&pat_msr, IA32_PAT_MT_UNCACHEABLE);
/* Add the WriteCombining cache type to the PAT */
ia32_pat_msr_ptr_set_pa4(&pat_msr, IA32_PAT_MT_WRITE_COMBINING);
ia32_wrmsr(IA32_PAT_MSR, pat_msr.words[1], pat_msr.words[0]);
x86_wrmsr(IA32_PAT_MSR, ((uint64_t)pat_msr.words[1]) << 32 | pat_msr.words[0]);
return true;
}

18
src/arch/x86/machine/hardware.c
View file

@ -21,9 +21,9 @@
BOOT_CODE void
init_sysenter_msrs(void)
{
ia32_wrmsr(IA32_SYSENTER_CS_MSR, 0, (uint32_t)SEL_CS_0);
ia32_wrmsr(IA32_SYSENTER_EIP_MSR, 0, (uint32_t)&handle_syscall);
ia32_wrmsr(IA32_SYSENTER_ESP_MSR, 0, (uint32_t)&ia32KStss.words[1]);
x86_wrmsr(IA32_SYSENTER_CS_MSR, (uint64_t)(word_t)SEL_CS_0);
x86_wrmsr(IA32_SYSENTER_EIP_MSR, (uint64_t)(word_t)&handle_syscall);
x86_wrmsr(IA32_SYSENTER_ESP_MSR, (uint64_t)(word_t)&ia32KStss.words[1]);
}
word_t PURE getRestartPC(tcb_t *thread)
@ -73,14 +73,14 @@ void flushCacheRange(void* vaddr, uint32_t size_bits)
assert(size_bits < WORD_BITS);
assert(IS_ALIGNED((uint32_t)vaddr, size_bits));
ia32_mfence();
x86_mfence();
for (v = ROUND_DOWN((uint32_t)vaddr, ia32KScacheLineSizeBits);
v < (uint32_t)vaddr + BIT(size_bits);
v += BIT(ia32KScacheLineSizeBits)) {
flushCacheLine((void*)v);
}
ia32_mfence();
x86_mfence();
}
/* Disables as many prefetchers as possible */
@ -96,19 +96,19 @@ disablePrefetchers()
WESTMERE_3_MODEL_ID, NEHALEM_1_MODEL_ID, NEHALEM_2_MODEL_ID, NEHALEM_3_MODEL_ID
};
version_info = ia32_cpuid_eax(0x1, 0x0);
version_info = x86_cpuid_eax(0x1, 0x0);
for (i = 0; i < ARRAY_SIZE(valid_models); ++i) {
if (MODEL_ID(version_info) == valid_models[i]) {
low = ia32_rdmsr_low(IA32_PREFETCHER_MSR);
high = ia32_rdmsr_high(IA32_PREFETCHER_MSR);
low = x86_rdmsr_low(IA32_PREFETCHER_MSR);
high = x86_rdmsr_high(IA32_PREFETCHER_MSR);
low |= IA32_PREFETCHER_MSR_L2;
low |= IA32_PREFETCHER_MSR_L2_ADJACENT;
low |= IA32_PREFETCHER_MSR_DCU;
low |= IA32_PREFETCHER_MSR_DCU_IP;
ia32_wrmsr(IA32_PREFETCHER_MSR, high, low);
x86_wrmsr(IA32_PREFETCHER_MSR, ((uint64_t)high) << 32 | low);
return true;
}