Commit graph

871 commits

Author SHA1 Message Date
Adrian Danis
2cfff40d9d Allow Arch_finaliseCap to return cleanup information
Changes Arch_finaliseCap and Mode_finaliseCap to return the same finaliseCap_ret_t type
as finaliseCap. This allows the Arch and Mode specific functions to define cleanup
information of its capabilities if necessary, just like the generic capabilities can
in finaliseCap.
2018-02-23 10:03:50 +11:00
Adrian Danis
d258cb3107 Generic postCapDeleted definition
Moves the explicit call of `deletedIRQHandler` in `emptySlot` into a new
`postCapDeleted` function that is a generic function to call after a capability
has been deleted.

Currently `deletedCap` only implementes the IRQ case.
2018-02-23 10:03:50 +11:00
Adrian Danis
d8ae122cc8 Generalise finaliseCap to more than just IRQs
Changes finaliseCap to return a generic definition of cleanup information that
needs to be done, instead of just encoding an IRQ number. The post deletion information
is encoded as a `cap_t` due to the capability type already being a union of all
the possible information. Aside from providing a properly generic mechanism the motivation
is to support a similar cleanup phase for I/O ports in the future.
2018-02-23 10:03:50 +11:00
Anna Lyons
e369263e40 Output core id in seL4_DebugDumpScheduler 2018-02-16 14:46:07 +11:00
Hesham Almatary
4812ddf440 SELFOUR-711: Add Eth/CPSW IO addresses to am335x platform 2018-02-13 15:00:28 +11:00
Adrian Danis
bae90533d9 x86: Fix flush RSB
The previous assembly is syntactically wrong and managed to somehow not get tested
originally
2018-02-07 10:20:14 +11:00
Adrian Danis
b1e799a447 x86: Config option for RSB flush on context switch
This option can be enabled to prevent a user from performing a Spectre like attack on
another user through polluting the RSB.
2018-02-02 10:23:31 +11:00
Adrian Danis
2423c62015 x86: Config option for branch prediction barrier on context switch
This option can be enabled to prevent a user from performing a Spectre like attack on
another user through polluting the indirect branch predictor.
2018-02-02 10:23:31 +11:00
Adrian Danis
f0594ac917 x86: Implement IBRS based Spectre mitigations
Provides the ability to enable the IBRS hardware Spectre mitigation strategies, as well
as completes the software mitigation by disabling jump tables in compilation. The
hardware mitigations are largely provided "for completeness" in the hopes that they
eventually become less expensive. For the moment there is no reason to turn on any
beyond STIBP if running in multicore
2018-02-02 10:23:31 +11:00
Adrian Danis
3900515c45 x86: Helpers for using the speculation MSRs 2018-02-02 10:23:31 +11:00
Adrian Danis
fe1302cb65 x86: Define MSRs for speculation control
These MSRs provide access to the IBRS feature and the IBPB command
2018-02-02 10:23:31 +11:00
Adrian Danis
caf456ddca x86: Helper for flushing RSB 2018-02-02 10:23:31 +11:00
Yanyan Shen
1936323e48 armv8: Add SMP support for aarch64
(1) Use NODE_STATE() to access per-core kernel data.
(2) Allocate kernel stack in src/arch/arm/64/head.S.
(3) Use the TPIDR_EL1 to contain the kernel stack pointer
    as well as the logical core ID. The kernel stack must
    be 4-KiB aligned, and the lowest 12 bits of TPIDR_EL1
    are for the logical core ID.
(4) Define the LD_EX, ST_EX, and OP_WIDTH as "ldxr", "stxr",
    and "w".
(5) Add irq_remote_call_ipi and irq_reschedule_ipi
2018-01-24 10:26:33 +11:00
Yanyan Shen
f92af27aec arm: add LD_EX, ST_EX, OP_WIDTH macros for ARM
The macros are used in try_arch_atomic_exchange function, and
they will be replaced by "ldrex", "strex", and null.
2018-01-24 10:18:02 +11:00
Yanyan Shen
13343815e3 armv8: add macro L1_CACHE_LINE_SIZE for aarch64 2018-01-24 09:35:50 +11:00
Adrian Danis
353e2aa38d x86: Define CR4 SMEP/SMAP bits 2018-01-18 10:51:53 +11:00
Adrian Danis
06671703cc x86: CPUID feature flags definition
Define the ebx result register for the extended feature flags CPUID
2018-01-18 10:23:34 +11:00
Adrian Danis
f26853b9a4 x86: Supervisor write protection
Prevents the kernel from writing to read only memory. This shouldn't happen, but catching
such attempts aids debugging and costs nothing to have neabled.
2018-01-18 10:22:40 +11:00
Bamboo
374da850af [STYLE_FIX] 2018-01-17 05:56:38 +00:00
Adrian Danis
29695d2636 x64: SKIM window to mitigate Meltdown (CVE-2017-5754) on x86-64
Introduces a kernel option that, when enabled, reduces the kernel window in a user address
space to just be Static Kernel Image and Microstate (SKIM), instead of the full kernel
address space. This isolates the important kernel data from the user preventing a
Meltdown style attack being able to violate secrecy. The kernel text and read only data,
i.e. anything that is static from boot, is not secret and can be allowed in the SKIM window
and potentially read by the user. Additionally to switch to and from the actual kernel
address space a small amount of state needs to also be in the SKIM window.

This is only an implementation for x86-64, although the same design is applicable to ia32
2018-01-17 16:38:52 +11:00
Adrian Danis
4a22471a62 x86: MSR for IA32_ARCH_CAPABILITIES and CPUID flag
Adds definitions for the IA32_ARCH_CAPABILITIES msr, as well as the CPUID leaf that
contains the feature flag for its existance.
2018-01-17 16:38:52 +11:00
Adrian Danis
ed37e31d5d x64: Invalid ASID with single asm block
This performs a double address space switch to invalidate an ASID using a single hand
written asm block instead of setCurrentCR3. The purpose of this is to ensure that the
only requirements on the temporary address space that we switch to is that the kernel
code is still mapped in at the same location. As we ensure our old cr3 value is in
register we can ensure, unlike with calling getCurrentCR3 that no stack or other
temporary memory is required.
2018-01-17 16:38:52 +11:00
Adrian Danis
43b4c5512b x86: Separate definition for kernel vspace root
Introduces a separate definition for vspace root that the kernel runs on. Having this
be distinct from the global vspace root allows for potential future distinction
between the global root (that is copied into all user address spaces) and the address
space that the kernel runs in.
2018-01-17 16:38:52 +11:00
Adrian Danis
6d1c8883e2 x64: Rename global paging structures to kernel
Currently the kernel address space and paging structures are used as the global ones.
This commit renames the paging structures from Global to Kernel to reflect this and
allows for separate global structures to be introduced in the future.
2018-01-17 16:38:52 +11:00
Adrian Danis
96842a2ca7 x64: If PCIDs are not enabled forbid them in any CR3 values
When PCIDs are not enabled the low 12 bits of CR3 are not all ignored as bits 3 and 4 control
memory typing of the translation. To prevent setting these to 'random' values we should leave
the low bits of CR3 0 when not using PCIDs.

A new makeCR3 wrapper is defined that is used instead of cr3_new that, based on CONFIG_SUPPORT_PCID,
either fills in the PCID or 0 as required.
2018-01-17 16:38:52 +11:00
Adrian Danis
4edbbbd4ed x64: Separate notion of current vspace root with current user vspace root
This introduces functions for specifically manipulating the user vspace root, either as an
abstract root or the specific CR3 value, in a way that is separated from the current vspace
root. Currently they are one and the same, but this separation allows for having the kernel
translation (and hence the active vspace root) be different the currently active user.
2018-01-17 16:38:52 +11:00
Adrian Danis
63198a7f10 x64: Align and pad node_info
node_info is a per-core data structure and should have always been padded and aligned to
a cache line to ensure there is no false sharing of cache lines
2018-01-17 16:38:52 +11:00
Adrian Danis
3a7fdde8b2 x86: Define per node arch global state
Global state in this context is state/datastructures that need to be available at all times,
both in user and kernel mode, by the hardware for correct operation. The purpose of creating
a separate per-node structure for it is so that there is the option of treating it specially
in the future from other per node state
2018-01-17 16:38:52 +11:00
Adrian Danis
a9dc424aa2 x64: Remove IRQ stack from per core data structure
The IRQ stack represents state that needs to be available in all contexts, both when user
code is running and when kernel code is running. Separating its definition from all the
other mode state provides the option in the future for treating it differently.
2018-01-17 16:38:52 +11:00
Adrian Danis
4857dcb000 x86: Separate header for TLB bitmap definitions
Having a separate header allows for them to be included into the platform hardware
definition without causing a circular include
2018-01-16 14:51:26 +11:00
Adrian Danis
b851560cf7 x64: Restrict user to non sign extended vaddr
This simplifies the kernel preventing the need to validate that addresses are canonical
on the return from syscalls and interrupts.
2018-01-16 11:33:29 +11:00
Adrian Danis
abe99d3ace x86: Export PMC to user
Provides an option that, on kernel init, enables user reading of the performance
monitoring counters. This is a step towards removing the dependence on
seL4_DebugRun for user level benchmarking/profiling
2018-01-15 15:46:25 +11:00
Adrian Danis
157d8577cc x86: CR4_PCE bit definition 2018-01-15 15:46:07 +11:00
Adrian Danis
c8eb525782 pc99: Make hardware.h usable from assembly
Rearranges hardware.h and makes use of the UL_CONST macro so that the header can be
included into assmebly files for its definitions
2018-01-09 14:13:41 +11:00
Adrian Danis
5247240a09 Implement UL_CONST macro for assembly and C
The UL_CONST macro provides a way to declare a constant that may or may not have a UL
suffix. In the case of assembly the UL suffix will be an error to many assemblers and
is not needed.
2018-01-09 14:13:41 +11:00
Adrian Danis
8d0b13c640 Token pasting helper
Adds utility macro for creating new tokens by token pasting
2018-01-09 14:13:41 +11:00
Adrian Danis
d43b717ef1 Move PAD_TO_NEXT_CACHE_LN to util.h
This utility macro is useful beyond just SMP code
2018-01-09 10:10:16 +11:00
Adrian Danis
570c1a65b0 Compile time abstraction for calling getCurrentCPUIndex
This defines a CURRENT_CPU_INDEX() macro that resolves to a constant 0 in the absence of
SMP, or a call to getCurrentCPUIndex in the presence of SMP. This provides a way to use
per-core data structures, without additional guards, in a way that is nearly invisible
to verification
2018-01-08 10:30:06 +11:00
Adrian Danis
252e0a82a7 aarch64: Declare base pointer size to be 48 bits to match x86
This matches the change in ee96314840
2017-12-20 16:13:43 +11:00
Adrian Danis
9f9578a7ae aarch64: Restrict USER_TOP to virtual addresses without high bits
Restricting virtual addresses to essentially be only addresses without bit 47 set
allows us to not need to check that an address passed in by the user is canonical
or not. Any address that is in danger of not being canonical (has bit 47 set but
not bits 48 to 63) will all by higher than USER_TOP and will not be permitted.
2017-12-20 16:11:06 +11:00
Adrian Danis
ee96314840 x64: Declare virtual addresses as 48-bits instead of 49-bits
In f6d367e8df virtual addresses were changed from 48
bits to 49 bits, but this does not seem necessary and the commit does not have enough
detail to justify the change. As such it is being changed back to 48 bits in this
commit, which is far less confusing and results on the bitfield generated functions
switching on bit 47 to determine sign extension (instead of bit 48), which matches
what the hardware description says should be done.
2017-12-19 16:13:08 +11:00
Anna Lyons
6d25d1e94a Fix armv6 CCNT definition 2017-12-19 13:46:09 +11:00
Adrian Danis
8639dbcaea Abstractly declare a threads registers have changed
This removes an #ifdef for x86-64 that was in generic code by declaring the generic
mechanism that is being used as an Arch_ function
2017-12-13 12:09:14 +11:00
Anna Lyons
8576758abf Define SchedulerAction_ChooseNewThread as 1
1 is never a valid tcb, and ~0 on x64 results in 0x00000000FFFFFFFF,
which could be a valid tcb.
2017-12-13 11:47:56 +11:00
Alexander Boettcher
734320d717 x86: add framebuffer info of MBI2 via boot_info 2017-11-30 22:54:01 +01:00
Alexander Boettcher
de610c22b6 x86: evaluate ACPI RSDP v1 multiboot 2 information 2017-11-28 16:25:07 +11:00
Alexander Boettcher
a4a52c5dcb pc99: Explicitly declare sizes for different versions of ACPI RSDP 2017-11-28 16:25:07 +11:00
Claudia Tu
1fc281e751 Add CONFIG_ to syscall.c and add missing include file 2017-11-28 14:24:40 +11:00
Bamboo
a32264bfb5 [STYLE_FIX] 2017-11-28 00:02:37 +00:00
Anna Lyons
cddc4e6ef5 Inline resetTimer for all platforms
- for arm generic timer platforms, we remove resetTimer ->
resetGenericTimer indirection and simply include generic_timer.h
- this reduces boiler plate for platforms that share timer drivers, as
  they simply include the one header
- there is far more timer code in the RT kernel, which motivates this
change
2017-11-28 10:21:46 +11:00