vcpu.c:
encapsulate inline assembly into inline functions that added to
device_pl2.h file.
other files:
replace #ifdef ARM_HYP with config_set(ARM_HYP)
machine_pl2.h:
new place for hyp mode inline functions.
boot.c:
replace #ifdef ARM_HYP with config_set(ARM_HYP).
vcpu.h, machine_pl2.h:
add empty functions when ARM_HYP is not defined to
pass compilation.
vcpu.c:
encapsulate inline assembly into inline functions that added to
device_pl2.h file.
other files:
replace #ifdef ARM_HYP with config_set(ARM_HYP)
machine_pl2.h:
new place for hyp mode inline functions.
boot.c:
replace #ifdef ARM_HYP with config_set(ARM_HYP).
vcpu.h, machine_pl2.h:
add empty functions when ARM_HYP is not defined to
pass compilation.
The functions pit_init and pit_wait_wraparound were previously marked as
PHYS_CODE, despite being called from BOOT_CODE elsewhere. This bug has
been present for some time but can be masked by the compiler inlining
all the involved functions, which is what typically happens.
Diminish rights were to prevent a user from sending a writeable
cap over a read only endpoint. It turns out this 'security' can
be worked around without difficulty (by putting caps in a cnode
and sending the cnode) making the current diminish rights
implementation functionally useless.
Removing diminish rights has the benefit of simplifying all the
IPC paths.
For x86-64, to disable IO instructions in user mode requires a
IO permission map being set up properly in TSS. Setting the
IO map base field of TSS larger than the TSS works for 32-bit, but
not 64-bit. This commit sets up a IO permission map usable for both
32-bit and 64-bit kernel and changes the TSS to use the mapping.
The IO permission bitmap is appened to the bitfield generated tss_t,
resulting the tss_io_t structure.
This is a stylistic commit to make names of variables/constants and
functions in the kernel more consistent. That is, things that are
not IA32 specific, but are generic x86, get renamed to having an
x86 name
when FS/GS_BASE_MSR are used to set the base addreses,
user applications should not touch FS/GS regiters; so
the kernel should load proper selectors once, establishing
limits and other attributes for the segments.
Current bootinfo defines two slot regions for paging structures,
one for page directories and one for page tables. This does not
easily generalise for N levels of paging structures. This change
uses a single region that has a known order of objects for however
many levels exist
Add platform dependent code (using macros from autoconf.h)
to make idle thread run in low power mode on all ARMv7
and ARMv6 except for the KZM board: That board does not
seem to support low power mode although the chip should,
according to he manual
Part of SELFOUR-419
Restructure the x86 interrupt handling to allow for a more flexible
method of using IOAPIC and MSI interrupts. The essence of this change
is to allow for the user to pick, for both IOAPIC and MSIs, which
CPU vector to use. Additionally there is future support, in the API,
for seL4 to eventually protect MSI interrupts with the vt-d interrupt
routing tables.
API behaviour for legacy systems using the PIC is preserved
Part of SELFOUR-281
This change brings the ia32 api in line with the planned x64 api,
which will have 12bits of ASID. Aside from providing a consistent
API, this change also frees up bits in the frame cap that will
allow further x64 changes to be unified.
Some versions of GCC replace a struct copy with a call to 'memcpy',
which it is fully in its rights to do. Unfortunately on ARM platforms,
that have no direct calls to memcpy, the optimizer (in the presence
of -fwhole-program) drops the implementation of memcpy, even as it
is outputting calls to it.
Add the USED attribute prevents the optimizer from dropping the
function eagerly.
