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2394 commits 1 branch 42 tags 18 MiB
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1003 commits

Author SHA1 Message Date
Anna Lyons
5cd0dd52be riscv: add missing fault types 2018-04-18 10:10:14 +10:00
Anna Lyons
00cf62bb09 riscv: remove unneccessary #if CONFIG_PT_LEVELS 
This guard is only required for object types to avoid
seL4 thinking they are valid objects. Defining the size constants does
not need to be guarded.
 2018-04-18 10:10:14 +10:00
Anna Lyons
308e8bf4d2 riscv: move machine functions to machine.h 
And add memory barriers while we are at it.
 2018-04-18 10:10:14 +10:00
Anna Lyons
952d305103 riscv: remove unused function 2018-04-18 10:10:14 +10:00
Adrian Danis
5ac36bcefb riscv: Move strcmp to util 2018-04-18 10:10:14 +10:00
Adrian Danis
c083919796 riscv: Move strlen to util 2018-04-18 10:10:14 +10:00
Adrian Danis
6938c98adf riscv: Fill physical memory regions from FDT 
Removes the hardcoded physical memory region from the spike platform and fills it from
FDT parsing instead.
 2018-04-18 10:10:14 +10:00
Adrian Danis
ee37eebcae riscv: Cleanup FDT code 
Rewrites the FDT code to remove all the disallowed function pointers have attempt to perform
the equivalent functionality of query_mem in place in the main parser. With the callback
system gone all the rest of the unused FDT code is deleted as it doesn't make sense.
 2018-04-18 10:10:14 +10:00
Adrian Danis
a2a6be95ca Define more freemem regions on all architectures except ARM 
2 freemem regions is far to prohibitive on platforms that have fragmented initial
memory. Ultimately ARM should be changed to also have more than 2, but is being
deferred for now as it will result in trivial verification breakage.
 2018-04-18 10:10:14 +10:00
Anna Lyons
f2214437ff riscv: remove unused function prototype 2018-04-18 10:10:14 +10:00
Anna Lyons
e17272fe4e riscv: remove concept of level in map functions 
It is no longer required
 2018-04-18 10:10:14 +10:00
Anna Lyons
a407e3ffd0 riscv: rewrite lookupPTSlot to decode bits 
- instead of specifying a level, find the leaf in the page table
- this simplifies a lot of the lookup code
 2018-04-18 10:10:14 +10:00
Adrian Danis
22b050c95d riscv: Redesign kernel window 
Restructures the kernel window so that instead of being a single contiguous region with
a single offset to physical memory, it is two such regions. This allows us to use the
larger of the two windows as a window into physical memory, and the second smaller window
as a place to run the kernel image from. Having this additional window allows us to
link the kernel for different physical addresses without needing to change its virtual
address, or change the layout of the kernel window.
There are other ways to achieve this, but this is one of the simplest and matches how
x86-64 implements its kernel window.
 2018-04-18 10:10:14 +10:00
Anna Lyons
a39ca9f15e riscv: remove safe mapping entries 
This is a concept from ARM that is not required for RISCV, as we are
only mapping one page at a time.
 2018-04-18 10:10:14 +10:00
Anna Lyons
4b555136ec riscv: remove incorrect comment about 4k frames 
they can be other sizes too
 2018-04-18 10:10:14 +10:00
Kent McLeod
a9085b3689 RISC-V: Guard __riscv_flen compiler definitions 
These definitions don't exist on software floatingpoint ABI's which is
what we are currently using
 2018-04-18 10:10:14 +10:00
Adrian Danis
61df56a7f3 riscv: Remove VMNoAccess mapping type 
A frame cannot be mapped without any access permissions, as this encoding is used to
represent a page table mapping.
 2018-04-18 10:10:14 +10:00
Anna Lyons
4f97ff1c93 riscv: remove unused benchmark code 2018-04-18 10:10:14 +10:00
Anna Lyons
23d83d6c42 riscv: remove capFTMapType 
it is not used on riscv
 2018-04-18 10:10:14 +10:00
Anna Lyons
0764d2ac7d riscv: build on 32 bit 2018-04-18 10:10:14 +10:00
Anna Lyons
937d042395 riscv: fix style 2018-04-18 10:10:14 +10:00
Anna Lyons
00cae0baed riscv: move STRINGIFY et al to util.h 2018-04-18 10:10:14 +10:00
Anna Lyons
d76511c7b4 riscv: address RVTODO in fastpath.h 2018-04-18 10:10:14 +10:00
Adrian Danis
80303364e8 riscv: Move implementations into c file 
Function implementations belong in source files, not header files.
 2018-04-18 10:10:14 +10:00
Adrian Danis
69d0e8bfa6 riscv: User registers in fastpath_restore 
Corrects the constraints to actually usage the assigned registers instead of dangerously
moving input registers into the desired register (that may be overwriting another input
register).
 2018-04-18 10:10:14 +10:00
Adrian Danis
55eca3e289 riscv: Add missing vspace prototypes 2018-04-18 10:10:14 +10:00
Adrian Danis
0b3f9e2d8d riscv: Correct implementation and usage of setVSpaceRoot 
setVSpaceRoot is declared in its function signature as taking a paddr, but neither
its implementation nor its usage respected this. The setVSpaceRoot signature was not
changed as its declared as a machine function and should be a minimal wrapper around
register manipulations and so it does make sense for it to take a paddr
 2018-04-18 10:10:14 +10:00
Adrian Danis
3da29df052 riscv: Prototype and guard Arch_userStackTrace 2018-04-18 10:10:14 +10:00
Adrian Danis
2ea1a326e0 riscv: Correct interrupt prototypes 2018-04-18 10:10:14 +10:00
Adrian Danis
58fa159860 riscv: Sanitize traps and fastpath functions 
This removes warnings by fixing prototypes of various traps and fastpath functions as well
as removing the use of custom sections.
 2018-04-18 10:10:14 +10:00
Adrian Danis
9b0056da89 riscv: remove HARTID 2018-04-18 10:10:14 +10:00
Adrian Danis
5505266a74 Remove irrelavant changes from riscv commit to non riscv arch code 2018-04-18 10:10:14 +10:00
Adrian Danis
1f74619db1 riscv: Correct prototype for decodeRISCVMMUInvocation 2018-04-18 10:10:14 +10:00
Adrian Danis
c825805658 riscv: Remove empty unused header 2018-04-18 10:10:14 +10:00
Adrian Danis
300c5a7ede riscv: Rationalize IO definitions 
This removes some duplicate (and incorrect) definitions that already exist in common
code and removes some unimplemented functions that are not used due to the current
absence of capDL dump support
 2018-04-18 10:10:14 +10:00
Anna Lyons
22fc329e1e riscv: add missing prototype for remap invocation 2018-04-18 10:10:14 +10:00
Hesham Almatary
6af207a078 RISC-V: Port FDT from riscv-pk (priv-1.10) 2018-04-18 10:10:14 +10:00
Adrian Danis
459eb10d66 riscv: Remove dead code 
These definitions match no existing kernel interface or abstraction and being removed
 2018-04-18 10:10:14 +10:00
Adrian Danis
4ebe773fb9 riscv: VMWriteOnly vm right 
Unlike other architectures riscv supports write only mappings and it simplifies management
of cap rights to actually support it.
 2018-04-18 10:10:14 +10:00
Adrian Danis
08433f89a5 riscv: Larger capFVMRights field 
We are going to increase the number of items the vm_rights_t enumeration and so this
field needs to be larger to hold those values.
 2018-04-18 10:10:14 +10:00
Adrian Danis
5b17cd9648 riscv: Missing arch cap abstractions 
These are needed after rebase
 2018-04-18 10:10:14 +10:00
Adrian Danis
aafa594258 RISCV: Place TODOs in the source 2018-04-18 10:10:14 +10:00
Hesham Almatary
83ba084713 [SELFOUR-1156] RISC-V Port 
Experimental release that supports both RV32 and RV64
 2018-04-18 10:10:14 +10:00
Yanyan Shen
f97604c34e armv8/hyp: Add VMID reuse code 2018-04-17 15:32:48 +10:00
Yanyan Shen
d23a02f3e4 armv8/hyp: Add HW ASID variables 2018-04-17 15:32:48 +10:00
Yanyan Shen
f7fd200255 armv8/hyp: Replace register strings with macros 2018-04-13 09:51:41 +10:00
Yanyan Shen
572daddc19 armv8/hyp: Define control register macros 2018-04-13 09:51:41 +10:00
Yanyan Shen
12c8fe62d8 armv8/hyp: Clarify SCTLR_EL1 macros 2018-04-13 09:51:41 +10:00
Yanyan Shen
280609cb60 armv8/hyp: Fix style 2018-04-13 09:51:41 +10:00
Yanyan Shen
dd51a8b414 armv8/hyp: sharable -> shareable 2018-04-13 09:51:41 +10:00