This commit provides a universal TLS_BASE virtual register on ARM, similar to as exists
on x86. Depending on the precise configuration this virtual register maps to a different
register
* aarch64: TPIDRURW is used for the TLS_BASE and is already declared and being saved
and restored on context switches, so this just adds TLS_BASE as an alias of it
* armv6: Has no hardware register for use for a TLS_BASE, and so the virtual register
gets stored into the globals frame
* armv7+: TPIDURO is used for TLS_BASE and so the restore paths are modified to load
TLS_BASE into it
Previously arm code assumed that either CONFIG_IPC_BUF_TPIDRURW or
CONFIG_IPC_BUF_GLOBALS_FRAME needed to be set. Given that neither of
these options are required for aarch64, remove this assumption and only
guard code with #ifdefs are required.
The following functions, readTTBR0, writeTTBR0, readTTBR1, and
writeTTBR1, write and return raw TTBR0/1 values.
The function writeTTBR0Ptr is added for used in context swtich
functions, and it modify the input physical address before
writing the TTBR0. Places using these functions are also
updated.
This commit saves/restores various control registers that can be
modified by guest VM kernels, so seL4 can execute multiple ARM
32-bit VMs multiplexing a single physical core.
When the CONFIG_HAVE_FPU option is selected, the commit allows
the VMs to use FPU registers and enables lazily saving/restoring
FPU registers for the VMs.
These arrays use to exist but are no longer used and array definitions such as
SYSCALL_MESSAGE are the new norm. As these have no meaning they are being deleted
to reduce confusion.
rpi3 documentation states RAM *should* be mapped from 0x00000000 onwards,
but we omit the start of physical memory as it caused early boot issues
on access. Instead use u-boot's default kernel load address as PHYS_BASE.
Several of the mapping calculations rollover when dealing with 32-bits due to the location
of memory on spike, the kernel/user window addresses, and the kernel load address.
Adjust the kernel window so that it covers the typical location of memory on
spike.
Changes the way IO ports work such that instead of 'minting' IO port caps down into new
IO port caps with smaller ranges new IO port ranges must be allocated centrally from
an IO port control cap. This mechanism acts in a very similar fashion as IRQ handler/control
capabilities and ensures that allocated IO ports do not overlap. Disallowing overlapping
IO ports is necessary to ensure the CDT remains valid as capabilities are deleted.
Refactors setIOPortMask to both be more efficient by never operating on individual bits,
whilst still having a structure that is more amenable to verification
Moves the function for manipulating a bitmap of IO ports from VCPU code into common
IO port code. This will be needed in the future by the IO Port control implementation
Revocability of a cap, with respect to its parent, is a general property on caps and
makes sense to be abstracted. This allows for the addition of an arch case without
further complicating the cteInsert function itself.
The TLB functions with "Local" postfix only execute on the
current calling core. The functions with the postfix
perform local operations and then IPI remote cores
to perform the same operations if necessary.
